Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-30
2001-04-24
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S625000, C438S648000, C438S656000, C438S685000
Reexamination Certificate
active
06221770
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to plasma-enhanced chemical vapor deposition (PECVD) for applying various film coatings to substrates, and more specifically to PECVD conducted at a low effective deposition temperature.
BACKGROUND OF THE INVENTION
In the formation of integrated circuits (IC's), thin films containing metal elements are often deposited upon the surface of a substrate, such as a semiconductor wafer. Thin films are deposited to provide conducting and ohmic contacts in the circuits and between the various devices of an IC. For example, a desired thin film might be applied to the exposed surface of a contact or via hole on a semiconductor wafer, with the film passing through the insulative layers on the wafer to provide plugs of conductive material for the purpose of making interconnections across the insulating layers.
One well known process for depositing thin metal films is chemical vapor deposition (CVD) in which a thin film is deposited using chemical reactions between various deposition or reactant gases at the surface of the substrate. In CVD, reactant gases are pumped into proximity with a substrate inside a reaction chamber, and the gases subsequently react at the substrate surface resulting in one or more reaction by-products which form a film on the substrate surface. Any by-products remaining after the deposition are removed from the chamber. While CVD is a useful technique for depositing films, many of the traditional CVD processes are basically thermal processes and require temperatures in excess of 1000° C. in order to obtain the necessary reactions. Such a deposition temperature is often far too high to be practically useful in IC fabrication due to the effects that high temperatures have on various other aspects and layers of the electrical devices making up the IC.
Certain aspects of IC components are degraded by exposure to the high temperatures normally related to traditional thermal CVD processes. For example, at the device level of an IC, there are shallow diffusions of semiconductor dopants which form the junctions of the electrical devices within the IC. The dopants are often initially diffused using heat during a diffusion step, and therefore, the dopants will continue to diffuse when the IC is subjected to a high temperature during CVD. Such further diffusion is undesirable because it causes the junction of the device to shift, and thus alters the resulting electrical characteristics of the IC. Therefore, for certain IC devices, exposing the substrate to processing temperatures of greater than 800° C. is avoided, and the upper temperature limit may be as low as 650° C. for other more temperature sensitive devices.
Furthermore, such temperature limitations may become even more severe if thermal CVD is performed after metal interconnection or wiring has been applied to the IC. For example, many IC's utilize aluminum as an interconnection metal. However, various undesirable voids and extrusions occur in aluminum when it is subjected to high processing temperatures. Therefore, once interconnecting aluminum has been deposited onto an IC, the maximum temperature to which it can be exposed is approximately 500° C., and the preferred upper temperature limit is 400° C. Therefore, as may be appreciated, it is desirable during CVD processes to maintain low deposition temperatures whenever possible.
Consequently, the upper temperature limit to which a substrate must be exposed precludes the use of some traditional thermal CVD processes which might otherwise be very useful in fabricating IC's. Titanium and titanium nitride are used in a variety of IC applications. It is frequently desired to form a titanium silicide contact layer over a silicon surface. This can be formed using chemical vapor deposition of titanium onto the silicon surface. The titanium silicide forms as the titanium is deposited. Further, in many applications a titanium nitride barrier layer is required prior to deposition of certain metal conductors such as aluminum or tungsten. ranium nitride can be deposited by chemical vapor deposition. The byproducts of the chemical vapor deposition—in particular, hydrogen chloride—act to etch the titanium contact layer. Therefore, the titanium must be nitrided prior to titanium nitride chemical vapor deposition.
Titanium nitride is frequently deposited onto aluminum as a contact layer. However, when titanium nitride is deposited onto aluminum, aluminum nitride is formed at the interface which acts as an insulator and impedes flow of current from one metalization layer to another. The titanium nitride is needed as an adhesion layer performing tungsten via plugs. To avoid this problem, a titanium layer is required to protect the aluminum and then permit sputter deposition of the titanium nitride adhesion layer.
To sputter deposit a film, the target is electrically biased and ions from the plasma are attracted to the target to bombard the target and dislodge target material particles. The particles then deposit themselves cumulatively as a film upon the substrate. Titanium may be sputtered, for example, over a silicon substrate after various contacts or via openings are cut into a level of the substrate. The substrate might then be heated to about 800° C. to allow the silicon and titanium to alloy and form a layer of titanium silicide (TiSi
2
). After the deposition of the titanium layer, the excess titanium is etched away from the top surface of the substrate leaving TiSi
2
at the bottom of each contact or via. A metal interconnection is then deposited directly over the TiSi
2
.
While physical sputtering provides deposition of a titanium film at a lower temperature, sputtering processes have various drawbacks. Sputtering normally yields very poor step coverage. Step coverage is defined as the ratio of film thickness on the bottom of a contact on a substrate wafer to the film thickness on the sides of the contact or the top surface of the substrate. Consequently, to sputter deposit a predetermined amount of titanium at the bottom of a contact or via, a larger amount of the sputtered titanium must be deposited on the top surface of the substrate or the sides of the contact. For example, in order to deposit a 200 Å film at the bottom of a contact using sputtering, a 600 Å to 1000 Å film layer may have to be deposited onto the top surface of the substrate or the sides of the contact. Since the excess titanium has to be etched away, sputtering is wasteful and costly when depositing layers containing titanium.
Furthermore, the step coverage of the contact with sputtering techniques decreases as the aspect ratio of the contact or via increases. The aspect ratio of a contact is defined as the ratio of contact depth to the width of the contact. Therefore, a thicker sputtered film must be deposited on the top or sides of a contact that is narrow and deep (high aspect ratio) in order to obtain a particular film thickness at the bottom of the contact than would be necessary with a shallow and wide contact (low aspect ratio). In other words, for smaller device dimensions in an IC, corresponding to high aspect ratio contacts and vias, sputtering is even more inefficient and wasteful. The decreased step coverage during sputter deposition over smaller devices results in an increased amount of titanium that must be deposited, thus increasing the amount of titanium applied and etched away, increasing the titanium deposition time, and increasing the etching time that is necessary to remove excess titanium. Accordingly, as IC device geometries continue to shrink and aspect ratios increase, deposition of titanium-containing layers by sputtering becomes very costly.
Further, sputter deposition requires the utilization of a separate reaction chamber. In applications where a first film is deposited by chemical vapor deposition, which is the preferred method, followed by sputter deposition of a second film, two different chambers are required. This could then be followed by a third chamber where, for example, a meta
Foster Robert F.
Hillman Joseph T.
Nguyen Tuan H.
Pham Thanhha
Tokyo Electron Limited
Wood Herron & Evans L.L.P.
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