Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2000-04-07
2003-06-24
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06582972
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to the fabrication of layered superlattice materials, and more particularly to a fabrication method that provides ferroelectric integrated circuit devices containing thin films of layered superlattice materials possessing high-polarizability, good coercive field values, and low-leakage current characteristics by using a low-temperature strong oxidizing agent, which decreases exposure to high temperatures and to oxygen at high temperatures during crystallization heating.
2. Statement of the Problem
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See Miller, U.S. Pat. No. 5,046,043. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Layered superlattice material oxides have been studied for use in integrated circuits. U.S. Pat. No. 5,434,102, issued Jul. 18, 1995, to Watanabe et al., and U.S. Pat. No. 5,468,684, issued Nov. 21, 1995, to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits. Layered superlattice materials exhibit characteristics in ferroelectric memories that are orders of magnitude superior to those of PZT and PLZT compounds.
A typical ferroelectric memory in an integrated circuit contains a semiconductor substrate and a metal-oxide semiconductor field-effect transistor (MOSFET) electrically connected to a ferroelectric device, usually a ferroelectric capacitor. Layered superlattice materials currently in use and development comprise metal oxides. In conventional fabrication methods, crystallization of the metal oxides to produce desired electronic properties requires heat treatments in oxygen-containing gas at elevated temperatures. The heating steps in the presence of oxygen are typically performed at a temperature in the range of 800° C. to 900° C. for 30 minutes to two hours. As a result of the presence of reactive oxygen at elevated temperatures, numerous defects, such as dangling bonds, are generated in the single crystal structure of the semiconductor silicon substrate, leading to deterioration in the electronic characteristics of the MOSFET. Good ferroelectric properties have been achieved in the prior art using process heating temperatures at about 700° C. to crystallize layered superlattice material. See U.S. Pat. No. 5,508,226, issued Apr. 16, 1996, to Ito et al. Nevertheless, the annealing and other heating times in the low-temperature methods disclosed in the prior art are in the range of three to six hours, which may be economically unfeasible. More importantly, the long exposure times of several hours in oxygen, even at the somewhat reduced temperature ranges, result in oxygen damage to the semiconductor substrate and other elements of the CMOS circuit.
After completion of the integrated circuit, the presence of oxides may still cause problems because oxygen atoms from a thin film of metal oxide layered superlattice material tend to diffuse through the various materials contained in the integrated circuit and combine with atoms in the substrate and in semiconductor layers, forming undesired oxides. The resulting oxides interfere with the function of the integrated circuit; for example, they may act as dielectrics in the semiconducting regions, thereby forming virtual capacitors. Diffusion of atoms from the underlying substrate and other circuit layers into the ferroelectric metal oxide is also a problem; for example, silicon from a silicon substrate and from polycrystalline silicon contact layers is known to diffuse into layered superlattice material and degrade its ferroelectric properties. For relatively low-density applications, the ferroelectric memory capacitor is separated from the CMOS circuit by a thick interlayer dielectric and is displaced to the side of the underlying CMOS circuit, and this may reduce somewhat the problem of undesirable diffusion of atoms between circuit elements. Nevertheless, as the market demand and the technological ability to manufacture high-density circuits increase, the distance between circuit elements decreases, and the problem of molecular and atomic diffusion between elements becomes more acute. To achieve high circuit density by reducing circuit area, the ferroelectric capacitor of a memory cell is placed virtually on top of the switch element, typically a field-effect transistor (hereinafter “FET”), and the switch and bottom electrode of the capacitor are electrically connected by a conductive plug. To inhibit undesired diffusion, a barrier layer is located under the ferroelectric oxide, between the capacitor's bottom electrode and the underlying layers. The barrier layer not only must inhibit the diffusion of oxygen and other chemical species that may cause problems; it must also be electrically conductive, to enable electrical connection between the capacitor and the switch. The maximum processing temperature allowable with current barrier technology is about 700° C. At temperatures above 700° C., the highest-temperature barrier materials degrade and lose their diffusion-barrier properties. On the other hand, the minimum feasible manufacturing process temperatures of layered superlattice materials used in the prior art is about 800° C., which is the temperature at which deposited layered superlattice materials, such as strontium bismuth tantalate, are annealed to achieve good crystallization.
For the above reasons, therefore, it would be useful to have a low-temperature method for fabricating layered superlattice materials in ferroelectric integrated circuits that minimizes the time of exposure to oxygen at elevated temperature, as well as reduces the maximum temperatures used.
SOLUTION
The embodiments of the present invention reduce fabrication processing temperatures and reduce the time of exposure of the integrated circuit to oxygen or other oxidizing gas at elevated temperature, that is, in the range of 500° C. to 700° C., while virtually eliminating heating of the integrated circuit at excessive temperatures, above 700° C.
Layered superlattice materials are metal oxides. An important feature of a method in accordance with the invention is the use of a strong oxidizing agent, or oxygen gas at a pressure greater than atmospheric pressure, during fabrication of a thin film of layered superlattice material. The term “strong oxidizing agent” herein means a substance that provides oxygen more readily than molecular oxygen gas, i.e., O
2
. The strong oxidizing agent serves to provide oxygen to a precursor thin film on an integrated circuit substrate. The oxygen is incorporated into the precursor thin film to enhance formation of metal oxide layered superlattice material. A precursor thin film, either liquid or solid, may be deposited on the integrated circuit substrate by a variety of techniques, including liquid spin-on, liquid-source misted chemical deposition (“LSMCD”), or metal organic chemical vapor deposition (“MOCVD”) methods.
In a method in accordance with the invention, a strong oxidizing agent is applied to a precursor thin film. It is a feature of the invention that the strong oxidizing agent is applied to the precursor thin film at a relatively low temperature. This is done for several reasons. Low temperature oxidation of the precursor thin film avoids oxidation damage of the semiconductor material or other elements of the integrated circuit that may occur under oxidizing conditions at the higher temperatures and longer heating times used in conventional methods. Also, the level of oxidation in the precursor thin film is thereby increased at the lower temperatures, before crystallization of the thin film at elevated temperature to form metal oxide layered superlattice material. As a result, the electronic characteristics of the layered superlattice material are improved compared to layered superlattice mate
Arita Koji
Celinska Jolanta
Joshi Vikram
McMillan Larry D.
Paz de Araujo Carlos A.
Chaudhuri Olik
Patton & Boggs LLP
Symetrix Corporation
Toledo Fernando
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