Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state – With a step of measuring – testing – or sensing
Reexamination Certificate
2006-05-12
2008-12-09
Kunemund, Robert M (Department: 1792)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
With a step of measuring, testing, or sensing
C117S089000, C117S094000, C117S095000, C117S096000
Reexamination Certificate
active
07462239
ABSTRACT:
Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
REFERENCES:
patent: 4210925 (1980-07-01), Morcom et al.
patent: 4749440 (1988-06-01), Blackwood et al.
patent: 4870030 (1989-09-01), Markunas et al.
patent: 5011789 (1991-04-01), Burns
patent: 5028973 (1991-07-01), Bajor
patent: 5129958 (1992-07-01), Nagashima et al.
patent: 5144376 (1992-09-01), Kweon
patent: 5158644 (1992-10-01), Cheung et al.
patent: 5211796 (1993-05-01), Hansen
patent: 5252841 (1993-10-01), Wen et al.
patent: 5285089 (1994-02-01), Das
patent: 5319220 (1994-06-01), Suzuki et al.
patent: 5323032 (1994-06-01), Sato et al.
patent: 5326992 (1994-07-01), Yoder
patent: 5373806 (1994-12-01), Logar
patent: 5378901 (1995-01-01), Nii
patent: 5380370 (1995-01-01), Niino et al.
patent: 5403434 (1995-04-01), Moslehi
patent: 5421957 (1995-06-01), Carlson et al.
patent: 5422502 (1995-06-01), Kovacic
patent: 5425842 (1995-06-01), Zijlstra
patent: 5470799 (1995-11-01), Itoh et al.
patent: 5496745 (1996-03-01), Ryum et al.
patent: 5508536 (1996-04-01), Twynam et al.
patent: 5512772 (1996-04-01), Maeda et al.
patent: 5517943 (1996-05-01), Takahashi
patent: 5557117 (1996-09-01), Matsuoka et al.
patent: 5557118 (1996-09-01), Hashimoto
patent: 5609721 (1997-03-01), Tsukune et al.
patent: 5670801 (1997-09-01), Nakano
patent: 5693147 (1997-12-01), Ward et al.
patent: 5729033 (1998-03-01), Hafizi
patent: 5783495 (1998-07-01), Li et al.
patent: 5859447 (1999-01-01), Yang et al.
patent: 5899752 (1999-05-01), Hey et al.
patent: 5926743 (1999-07-01), Xi et al.
patent: 5986287 (1999-11-01), Eberl et al.
patent: 5998305 (1999-12-01), Holmer et al.
patent: 6031255 (2000-02-01), Delage et al.
patent: 6043519 (2000-03-01), Shealy et al.
patent: 6049098 (2000-04-01), Sato
patent: 6058945 (2000-05-01), Fujiyama et al.
patent: 6060397 (2000-05-01), Seamons et al.
patent: 6074478 (2000-06-01), Oguro
patent: 6164295 (2000-12-01), Ui et al.
patent: 6190453 (2001-02-01), Boydston et al.
patent: 6221168 (2001-04-01), Carter et al.
patent: 6316795 (2001-11-01), Croke, III
patent: 6391796 (2002-05-01), Akiyama et al.
patent: 6454854 (2002-09-01), Ose
patent: 6566279 (2003-05-01), Suemitsu et al.
patent: 6593211 (2003-07-01), Sato
patent: 7108748 (2006-09-01), Brabant et al.
patent: 1987-022420 (1987-01-01), None
patent: 1989-004015 (1989-01-01), None
patent: 1995-153685 (1995-06-01), None
patent: 1999-040506 (1999-02-01), None
Wolansky et al., “Low temperature clean for Si/SiGe epitaxy for CMOS integration of heterojunction bipolar transistors,” Proceedings of the 8thInternational Symposium on Silicon Materials Science and Technology, vol. 1, pp. 812-821 (1989).
Wolf et al., Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, USA, pp. 140-142, 155-156, 1986.
Wolf et al., Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, USA, pp. 225-264, 2000.
Brabant Paul D.
Italiano Joe P.
Wen Jianqing
ASM America Inc.
Knobbe Martens Olson & Bear LLP
Kunemund Robert M
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