Low temperature formation of palladium silicided shallow junctio

Details Low temperature formation of palladium silicided shallow junctio Low temperature formation of palladium silicided shallow junctio

1995-05-24

1997-04-29

Quach, T. N.

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Diffusing a dopant

438533, 438682, 438659, H01L 21225, H01L 21283

Patent

active

056248679

ABSTRACT:
A low temperature process for forming palladium silicided shallow junctions in which ions are implanted into a palladium or a palladium silicide layer over a silicon substrate. The impurities are driven into the silicon substrate during the formation or recrystallization of the palladium silicide layer, and a diffusion region with shallow junction is formed in the substrate.

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patent: 5268317 (1993-12-01), Schwalke et al.
Lin, C.T., et al., "Low Temperature formation of Shallow p.sup.+ n Junctions . . . ," J. Electrochem. Soc., vol. 142, No. 5, May 1995, pp. 1579-1584.
Yamada, K., et al., "Formation of Metal silicide-silicon . . . ,"Appl. Phys. Lett, vol. 64, No. 25, 20 Jun. 1994, pp. 3449-3351.
Kang, S., et al., "Effects of amorphous silicon capping . . . ,"Appl. Phys. Lett., vol. 54, No. 8, 20 Feb. 1989, pp. 693-695.

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