Low temperature BPSG deposition process

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

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438787, 438790, H01L 2131, H01L 21469

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active

060135832

ABSTRACT:
A process for the low temperature deposition of a thin film of borophosphosilicate glass ("BPSG") for use in semiconductor devices, such as DRAMs, is disclosed. The process includes utilizing R--OH groups as reagents to provide additional --OH groups so that an intermediate {Si(OH).sub.4 }.sub.n is formed having superior reflow properties so that the annealing and reflow steps may occur at temperatures less than 750.degree. C., which is the current processing temperature.

REFERENCES:
patent: 3447958 (1969-06-01), Okutsu et al.
patent: 4371587 (1983-02-01), Peters
patent: 4413022 (1983-11-01), Suntola et al.
patent: 4683144 (1987-07-01), Nishimura et al.
patent: 4835597 (1989-05-01), Okuyama et al.
patent: 5094984 (1992-03-01), Liu et al.
patent: 5104482 (1992-04-01), Monkowski et al.
patent: 5166101 (1992-11-01), Lee et al.
patent: 5225378 (1993-07-01), Ushikawa
patent: 5231058 (1993-07-01), Maeda et al.
patent: 5296400 (1994-03-01), Park et al.
patent: 5314724 (1994-05-01), Tsukune et al.
patent: 5372958 (1994-12-01), Miyasaka et al.
patent: 5387546 (1995-02-01), Maeda et al.
patent: 5405489 (1995-04-01), Kim et al.
patent: 5405802 (1995-04-01), Yamagata et al.
patent: 5409743 (1995-04-01), Bouffard et al.
patent: 5409858 (1995-04-01), Thakur et al.
The Anisotropic Deposition of Doped Silicate Glass; Uram, et al.,; Lam Research Corp.; J. Electrochem. Soc., vol. 140, No. 12, Dec. 1993.
Nguyen, et al. "Boron Phosphorous Silicon Glass Insulator for Sub-Half Micron Trench Fill," Electrochemical Society extended abstract #251, Spring 1994, pp. 406-407.
Matsuura, et al. "Novel Self-Planarizing CVD Oxide for Interlayer Dielectric Applications," IEDM Technical Digest, 1994, pp. 117-120.
C. Dobson, et al., Advanced SiO2 Planarization Using Silane and H202, Semiconductor International, Dec. 1994, vol. 17, No. 14, pp. 85-86, 88 XP000671223.
Patent Abstracts of Japan, vol. 018, No. 035 (E-1494), Jan. 19, 1994 & JP 05 267480 A (Ricoh Co Ltd), Oct. 15, 1993, abstract.
Patent Abstracts of Japan, vol. 015, No. 058 (E-1032), Feb. 12 1991 & JP 02 284425 A (NEC Corp), Nov. 21, 1990, abstract.

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