Low switching power limited switch dynamic logic

Details Low switching power limited switch dynamic logic Low switching power limited switch dynamic logic

2005-09-06

2005-09-06

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S097000, C326S098000

Reexamination Certificate

active

06940312

ABSTRACT:
An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.

REFERENCES:
patent: 6496038 (2002-12-01), Sprague et al.
patent: 6717442 (2004-04-01), Campbell

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