Low-swing interconnections for field programmable gate arrays

Details Low-swing interconnections for field programmable gate arrays Low-swing interconnections for field programmable gate arrays

2005-08-24

2008-08-26

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C326S047000, C326S113000

Reexamination Certificate

active

07417454

ABSTRACT:
An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.

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Rabaey, Jan M. et al.; “Digital Integrated Circuits”, A Design Perspective, 2003, Ch. 5, pp. 214-219, 2nd Ed., available from Prentice Hall Electronics and VLSI Series, 800 East 96th Street Indianapolis, Indiana, month N/A.

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