Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-11
2003-09-09
Meier, Stephen D. (Department: 2836)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S360000, C257S546000
Reexamination Certificate
active
06617649
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains in general to a semiconductor circuit, and, more particularly, to an electrostatic discharge protection circuit incorporating bi-directional silicon diodes.
BACKGROUND OF THE INVENTION
A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is provided to the IC. In addition, an ESD event can occur between (a) a pin of the IC and VSS (ground), (b) between a pin and VDD (power), (c) among different pins of the IC, and (d) between VDD and VSS, as shown in
FIGS. 1A-1D
, respectively. Common sources of ESD include personnel and processing equipment. It is known that the susceptibility of a device to an ESD event may be determined by simulations with one of three models, Human Body Model (HBM), Machines Model (MM) and Charged Device Model (CDM). These models, although do not necessarily simulate the susceptibility of real life situations, are used to establish baselines of susceptibility data.
The ESD Association Standard for the Development of an Electrostatic Discharge Control Program for—Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Device), ANSI/ESD-S20.20-1999 (Aug. 4, 1999), provides for ESD sensitivity testings for each of the three models. The HBM model represents the discharge from the fingertip of a standing individual delivered to the conductive leads of the device.
FIG. 2
shows an HBM model ESD test circuit, modeled by a 100 pF capacitor, representing the effective capacitance of the human body, discharged through a switching component and 1,500 ohm series resistor, representing the effective resistance of the human body, into the device under tests. The discharge is a double exponential waveform with a rise time of 2-10 nanoseconds (nS) and a pulse duration of approximately 150 nS. Similar testing parameters are set forth in MIL-STD-883E method 3015.7 (Mar. 22, 1989), and JEDEC Standard for Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), JESD22-A114-B (June 2000). An example discharge voltage is approximately 2,000 volts at a peak current of approximately 1.33 amperes (A).
The MM model represents a rapid discharge from items such as a charged board assembly, charged cables, or the conduction arm of an automatic tester. The effective capacitance is approximately 200 pF discharged through a 500 nH inductor directly into the device because the effective resistance of the machine is approximately zero. The discharge is a sinusoidal decaying waveform having a peak current of approximately 8 A with a rise time of 5-8 nS and a period of approximately 80 nS. The MM model is also described in EIA/JEDEC Standard, Test Method A115-A for Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM), EIA/JESD22-A115-A (October 1997).
The CDM model is device dependent, and describes a phenomenon when a device acquires charge through frictional or electrostatic induction processes and then abruptly touches a grounded object or surface. The waveform rise time is generally less than 200 picoseconds, and the entire ESD event can take place in less than 2.0 nS. Current levels can reach several tens of amperes during discharge. The CDM model is also described in JEDEC Standard, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components, JESD22-C101-A (June 2000).
The ESD Association Standard for the Development of an Electrostatic Discharge Control Program for—Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Device), ANSI/ESD-S20.20-1999 (Aug. 4,1999), MIL-STD-883E method 3015.7 (Mar. 22, 1989), JEDEC Standard for Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), JESD22-A114-B (June 2000), EIA/JEDEC Standard, Test Method A115-A for Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM), EIA/JESD22-A115-A (October 1997), and JEDEC Standard, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components, JESD22-C101-A (June 2000) are hereby incorporated by reference.
In commercial applications, a device is expected to withstand ±2,000 volts in ESD for HBM models, ±200 volts for MM models, and ±1000 volts for CDM models.
FIG. 3
is a plot that shows the characteristics of HBM, MM and CDM discharges. As shown in
FIG. 3
, the CDM discharge reaches a peak current of approximately 15A in less than 1 nS, and the discharge is complete within approximately 10 nS.
Many schemes have been implemented to protect an IC from the three modeled ESD events. A common protection scheme is using a parasitic transistor associated with an n-type metal-oxide semiconductor (MOS) with the source coupled to ground and the drain connected to the pin of the ESD protection device. Diodes or diode-coupled transistors have been used for ESD protection in radio-frequency (RF) applications. In a RF IC, an on-chip ESD circuit should ideally provide robust ESD protection, while exhibiting minimum parasitic input capacitance and low voltage-dependency. In a deep-submicron complementary metal-oxide semiconductor (CMOS) process technology with shallow-trench isolations (STIs), a diode has been used for ESD protection and is generally formed contiguous with either an N
+
or P
+
diffusion region in a semiconductor substrate.
FIG. 4A
shows a cross-sectional view of a known diode ESD protection structure formed in an IC. Referring to
FIG. 4A
, a P
+
diffusion region is bound by STIs on either side, and therefore the diode formed by the STI is also known as an STI-bound diode. The STI-bound diode exhibits a bottom capacitance, C
bottom
. However, an STI-bound diode has been found to have significant leakage current due to an interference between a silicide layer (not shown) of the P
+
diffusion region and the STIs around the P
+
region.
FIG. 4B
shows a cross-sectional view of another known diode ESD protection structure, known as a polysilicon-bound diode, introduced to address the leakage current problem with an STI-bound diode. The P
+
diffusion region in a polysilicon-bound diode is now defined by a polysilicon gate, and therefore the leakage current from the edges of STIs is eliminated. However, the total parasitic capacitance of the polysilicon-bound diode is larger than that of the STI-bound diode because of the addition of the sidewall junction capacitance of the P
+
diffusion region.
FIG. 5
is a circuit diagram showing a known ESD protection scheme using dual diodes. Referring to
FIG. 5
, the combination of the dual-diode structures and VDD-to-VSS ESD clamp circuit provides a path for an ESD current
2
to discharge, instead of through the internal circuits. When ESD current
2
is provided to a signal pad PAD
1
, and with a signal pad PAD
2
relatively grounded, ESD current
2
is conducted to VDD through Dp
1
. ESD current
2
is discharged to VSS through the VDD-to-VSS ESD clamp circuit and flows out of the IC from Dn
2
to PAD
2
. Diode Dp
1
has a capacitance of Cp
1
and diode Dn
1
has a capacitance of Cn
1
. The total input capacitance C
in
primarily comes from the parasitic junction capacitance of diodes, and is calculated as follows:
C
in
=Cp
1
+Cn
1
wherein Cp
1
and Cn
1
are parasitic junction capacitances of diodes Dp
1
and Dn
1
, respectively.
FIG. 6
is a plot showing the relationship between a pad voltage and parasitic input capacitance of the circuit shown in FIG.
5
. Referring to
FIG. 6
, when the voltage on the pad increases, the parasitic junction capacitance of Dp
1
increases and the parasitic junction capacitance of Dn
1
decreases. Therefore, the total input parasitic capacitance C
in
is nearly co
Chang Chyh-Yih
Ker Ming-Dou
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Industrial Technology Research Institute
Meier Stephen D.
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