Low stress and warpage laminate flip chip BGA package

Details Low stress and warpage laminate flip chip BGA package Low stress and warpage laminate flip chip BGA package

2006-03-07

2006-03-07

Clark, S. V. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Die bond

C257S707000, C438S118000

Reexamination Certificate

active

07009307

ABSTRACT:
Provided are a semiconductor die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the die and packaging substrate. In general, the modulus of the adhesive, which is used to attach the heat spreader to the substrate, is selected to provide a relatively “soft” connection. The result is a package with less bowing and so improved co-planarity (e.g., in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the die and package reliabilities are thereby enhanced.

REFERENCES:
patent: 5015803 (1991-05-01), Mahulikar et al.
patent: 5909056 (1999-06-01), Mertol
patent: 6015722 (2000-01-01), Banks et al.
patent: 6091603 (2000-07-01), Daves et al.
patent: 6103550 (2000-08-01), Camenforte et al.
patent: 6104093 (2000-08-01), Caletka et al.
patent: 6262489 (2001-07-01), Koors et al.
patent: 6472762 (2002-10-01), Kutlu
patent: 6504242 (2003-01-01), Deppisch et al.
patent: 6566748 (2003-05-01), Shimizu et al.
patent: 6617683 (2003-09-01), Lebonheur et al.
patent: 6621160 (2003-09-01), Shibamoto et al.
patent: 6744132 (2004-06-01), Alcoe et al.
patent: 6756685 (2004-06-01), Tao
patent: 6773963 (2004-08-01), Houle
patent: 6784535 (2004-08-01), Chiu
patent: 6784541 (2004-08-01), Eguchi et al.
patent: 6909176 (2005-06-01), Wang et al.
patent: 2004/0016996 (2004-01-01), Tang
patent: 2004/0150118 (2004-08-01), Honda
patent: 2004/0155358 (2004-08-01), Iijima
patent: 2004/0188862 (2004-09-01), Nagarajan et al.
U.S. Appl. No. 10/305,671 filed on Nov. 25, 2002 entitled “Flip Chip Package With Warpage Control”.
U.S. Appl. No. 10/719,451 filed Nov. 20, 2003 entitled “Structure And Material For Assembling A Low-K Si Die To Achieve A Low Warpage And Industrial Grade Reliability Flip Chip Package With Organic Substrate”.
Office Action, 12 page document dated Oct. 20, 2004, U.S. Appl. No.: 10/305,671.

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