Low stress and low profile cavity down flip chip and wire...

Details Low stress and low profile cavity down flip chip and wire... Low stress and low profile cavity down flip chip and wire...

1999-10-29

2002-07-02

Gaffin, Jeffrey (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S764000, C361S690000, C361S692000, C361S807000, C361S809000, C257S778000

Reexamination Certificate

active

06414849

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit packaging, and in particular to flip-chip and wire bond ball grid array (BGA) integrated circuit packages. Still more particularly, the present invention relates to forming a low stress and low profile cavity down flip chip and wire bond BGA package.
2. Description of the Related Art
Integrated circuit packaging technology is becoming a somewhat limiting factor in development of higher performance, packaged integrated circuits. Package designers are struggling to keep pace with the increase in pin count, size limitations, low profile mounting constraints, and other evolving requirements for packaging and mounting integrated circuits. One common packaging and package mounting solution currently being utilized is a ball grid array (BGA) package, in which an array of selective solderable areas for solder balls (or “bumps”) are formed on the integrated circuit package. Conductive leads or traces on the package connect the selective solderable areas to wire bond sites for wire bonds connecting to the integrated circuit die within the package. A corresponding array of selective solderable areas are formed on a printed circuit board (PCB) substrate on which the packaged integrated circuit is to be mounted and connect, with conductive traces or leads, to other discrete or integrated circuit devices or to connector pins or edge connectors on the printed circuit board. Solder balls or bumps are formed on the selective solderable areas in the grid array of either the package or the PCB substrate, placed over the corresponding selective solderable areas in the other grid array, and then heated to a temperature sufficient to melt the solder balls and solder the package to the PCB substrate.
Within the integrated circuit package, the integrated circuit die is placed on a package substrate or within a cavity in a die carrier (which often also serves a heat sink or heat spreader). Wire bonds are formed connecting bonds pads on the integrated circuit die to corresponding nearby wire bond sites on the package substrate or die carrier, which are connected in turn by conductive traces or leads to selective solderable areas for solder bumps. The selective solderable areas on the package substrate or die carrier may be either on the same major surface of the package substrate or die carrier as the cavity and/or integrated circuit die, for mounting the packaged integrated circuit “cavity down” on the PCB substrate, or on the opposite major surface (or “side”) from the cavity, for mounting the packaged integrated circuit “cavity up” on the PCB substrate. When the selective solderable areas on the die carrier are located on the opposite side of the package substrate die carrier from the die cavity, the conductive traces connecting the selective solderable areas to the wire bond sites near the cavity may pass through the package substrate or die carrier or around one or more edges of the package substrate or die carrier.
FIG. 1
illustrates a thin fine-pitch BGA (TFBGA) wire bond package
102
which, with respect to the present invention, represents a relatively early stage in the evolution of BGA packages. TFBGA package
102
includes a multilayer printed circuit board (PCB) substrate
104
having a first layer
106
of conductive traces and a second layer
108
of conductive traces on opposite sides of and separated by one or more insulating layer(s)
110
. Plated through holes
112
are arranged throughout multilayer PCB substrate
104
to electrically connect wire bonding sites
106
a
-
106
n
in the first layer
106
to conductive traces in the second layer
108
, with bonding wires
114
extending between wire bonding sites
116
and corresponding bond pads
118
arranged upon the integrated circuit die
120
. Integrated circuit die
120
is held in place upon PCB substrate
104
by a layer of adhesive
122
, typically silver epoxy glue, and integrated circuit die
120
, adhesive
122
, bonding wires
114
, wire bonding sites
116
, and bond pads
118
are all enclosed by an encapsulating cap
124
, such as a hardened plastic resin. By conventional solder-bumping and reflow processes, a plurality of solder balls
126
are arranged in a grid array on the opposite side of PCB substrate
104
from integrated circuit die
120
and attached to conductive traces
108
. Solder balls
126
are then electrically connected to a solder ball attachment sites
128
on a main PCB
130
, which may be any of a large variety of integrated circuit cards such as motherboards, adapter cards, and the like. TFBGA package
102
is typically about 1.15 millimeters (mm) thick, although the thickness may range from about 1.07 mm to about 1.23 mm.
FIG. 2
illustrates an ultra fine-pitch BGA (UFBGA) wire bonded package
202
, the successor to TFBGA package
102
in the evolution of BGA packages. UFBGA package
202
includes a single-layer printed circuit board (PCB) substrate
204
having a metal tape layer
206
and plated through holes
208
arranged throughout PCB substrate
204
to electrically connect wire bonding sites
210
on an upper surface of PCB substrate
204
to conductive traces
212
on a lower surface of PCB substrate
204
. Bonding wires
214
extend between and connect wire bonding sites
210
and bond pads
216
on the integrated circuit die
218
. The remaining features of UFBGA package
202
parallel corresponding features of TFBGA package
102
in
FIG. 1
, except UFBGA package
202
is typically only about 0.93 mm thick, and generally no less than about 0.86 mm and no more than about 1.00 mm in thickness. This package style is thinner than TFBGA and is the preferred design for miniaturization.
Solder balls or bumps may also be employed in arrays in mounting integrated circuit die (or “chips”) to the die carrier for thin packages. Bumped silicon chips, often referred to as “flip-chips” since they are mounted with the active layer side of the die adjacent to the die carrier rather than the backside, use a solder bump or ball to solder the electrical connections that interconnect integrated circuits within the die to conductive leads on the die carrier. Solder bumps or balls allow direct coupling between the pads on the silicon chip in which the integrated circuit is formed and matching contacts on the die carrier or package substrate. The flip-chip is aligned to the die carrier or package substrate and all connections are made simultaneously by reflowing the solder. A polymer underfill within the gap between the silicon chip and the package substrate is formed following reflow of the solder bumps to increase the mechanical integrity and reliability of integrated circuit packages.
FIG. 3
illustrates a thin fine-pitch BGA (TFBGA) flip-chip package
302
, which followed and overlapped TFBGA and UFBGA wire bond packages in the evolution of BGA packages. Flip chip package
302
includes a single-layer printed circuit board (PCB) substrate
304
, typically copper plated on both sides to receive solder balls
306
on conductive traces
308
disposed upon a lower surface
310
as well as smaller solder balls
312
at bonding sites
314
on an upper surface
316
of PCB substrate
304
. Solder balls
306
and small solder balls
312
are arranged in a grid array and attached to conductive traces
308
and bonding sites
314
by conventional solder-bumping and reflow processes.
In flip-chip package
302
, an integrated circuit die
318
is “inverted” and electrically connected at the surface of an “upper” or active layer to PCB substrate
304
via small solder balls
312
as described above. Afterwards an underfill material
320
, typically epoxy, is disposed in all of the void space between integrated circuit die
318
and PCB substrate
304
. Solder balls
306
are then electrically connected to solder ball attachment sites
322
on main PCB
324
. Thus, flip-chip package
302
does not require bonding wires, and has a total typical thickness of about 1.14 mm, or within the range of about 1.07

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