Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-29
2001-05-01
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000
Reexamination Certificate
active
06225666
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device structures and, in particular, to active area silicon island structures for use in semiconductor devices and methods for their manufacture.
2. Description of the Related Art
The manufacturing of semiconductor devices (e.g. MOS transistors, bipolar transistors, diodes, capacitors, resistors, etc.) typically involves their formation in, and on, an area of a silicon substrate that is known as the “active area silicon island” or simply “active area.” An individual active area silicon island, and its associated semiconductor device(s), is customarily isolated from neighboring active area silicon islands by electrical isolation regions. A combination of an active area silicon island and its associated electrical isolation region can be designated as an active area silicon island structure. In deep sub-micron semiconductor device manufacturing, Shallow Trench Isolation (STI) processes are the most common method of forming active area silicon island structures.
In a conventional STI process, a trench with an essentially rectangular cross-section profile is first etched into a silicon substrate
10
. A silicon dioxide (SiO
2
) layer is subsequently deposited on the silicon substrate
10
(typically using a relatively expensive high density plasma-based [HDP] technique) and planarized to form a silicon dioxide (SiO
2
) electrical isolation region
12
and active area silicon island
16
, as shown in FIG.
1
. The result of a conventional STI process is the formation of an active area silicon island structure
18
with relatively sharp corners
20
,
22
,
24
and
26
at the top and the bottom of the interface between the SiO
2
electrical isolation region
12
and the active area silicon island
16
.
The corners
20
,
22
,
24
and
26
are an artifact of the essentially rectangular cross-section profile of both the active area
16
and the SiO
2
electrical isolation region
12
. These relatively sharp corners create a high mechanical stress in the active area silicon island that can lead to a reduction in the integrity of a silicon dioxide gate subsequently grown thereon. Even if costly and time consuming procedures are implemented to (a) etch a trench with a slight sidewall angle (as a precursor to an active area with an essentially quadrilateral cross-section profile) or to (ii) lessen the sharpness of the corners
20
,
22
,
24
and
26
through a rounding of their profile, an undesirably high mechanical stress is still often present in active area silicon islands formed using conventional STI processes.
In addition, if the silicon dioxide layer is over-planarized, such that the upper surface of the resulting SiO
2
electrical isolation region
12
is below the upper surface of the active area silicon island
16
, a subsequently deposited polysilicon gate layer can “wraparound” the top corners
20
and
22
of the active area silicon island
16
. This “wraparound” can result in an undesirable transistor electrical phenomena known as “double hump” and/or short circuits between neighboring semiconductor devices due to the presence of polysilicon gate layer stringers. For a further discussion of the requirements and drawbacks of conventional STI processes, see M. Nandakumar et al.,
Shallow Trench Isolation for Advanced ULSI CMOS Technologies
, IEDM, 133-136 (1998), which is hereby fully incorporated by reference.
U.S. Pat. No. 4,698,316 to Corboy, Jr. et al. and U.S. Pat. No. 5,592,792 to Corboy, Jr. et al., both of which are hereby incorporated by reference, describe epitaxial silicon deposition methods for the formation of “silicon islands” within the apertures of a silicon dioxide masking layer. The resulting silicon islands have a rectangular cross-section profile and are, therefore, subject to an undesirably high mechanical stress in a similar manner to active area silicon island structures formed using conventional STI processes.
Still needed in the art is an active area silicon island structure with low mechanical stress that is not susceptible to polysilicon gate layer “wraparound” or polysilicon gate layer stringer formation. Also needed is a process for its manufacture that is simple, inexpensive and compatible with standard semiconductor device processing.
SUMMARY OF THE INVENTION
The present invention provides a low stress active area silicon island structure with a reduced susceptibility to polysilicon gate layer “wraparound” and polysilicon gate layer stringer formation. An active area silicon island structure according to the present invention includes a semiconductor substrate (typically a silicon wafer) with an electrical insulation layer (formed, for example, of SiO
2
, silicon nitride, or other dielectric material) disposed thereon. The electrical insulation layer has at least one active area opening therein that extends from the upper surface of the electrical insulation layer to the surface of the semiconductor substrate. An active area silicon island fills the active area opening. A cross-section of the active area silicon island, perpendicular to the surface of the semiconductor substrate, has a non-rectangular profile, such as a “wineglass ” profile.
The non-rectangular profile of the active area silicon island provides an active area silicon island structure with relatively low mechanical stress, in comparison to the mechanical stress that is induced by the essentially rectangular profiles created by conventional STI processes. The relatively low mechanical stress is due, at least in part, to the absence of sharp corners at the top of the active area silicon island. One of ordinary skill in the art will recognize upon reading this disclosure, therefore, that the non-rectangular profile of active area silicon islands in structures according to the present invention encompasses (i) non-quadrilateral profiles, (ii) profiles wherein a major portion of the profile is curved (e.g. a wine-glass profile), and (iii) all other profiles that do not include sharp corners located, at least, in the proximity of the top of the active area silicon island.
The invention also provides a process for the formation of a low stress active area silicon island structure. The process first includes providing a semiconductor substrate, followed by forming an electrical insulation layer (e.g. a silicon dioxide or silicon nitride layer) thereon. At least one active area opening is then created in the electrical insulation layer, extending from the upper surface of the electrical insulation layer to the surface of the semiconductor substrate. A cross-section of the active area opening, taken perpendicular to the surface of the semiconductor substrate, has a nonrectangular profile, such as a wine-glass profile. Next, an active area silicon layer is deposited, using a selective epitaxial silicon deposition process, to fill the active area opening and cover the electrical insulation layer. The active area silicon layer is subsequently removed from the electrical insulation layer, as well as from the above the active area opening, while leaving the active area silicon layer in the active area opening. The removal of the active area silicon layer from the electrical insulation layer and from the above the active area opening results in the formation of an active area silicon island, in the active area opening, that has a cross-section (perpendicular to the surface of the semiconductor substrate) with a non-rectangular profile.
REFERENCES:
patent: 4183134 (1980-01-01), Oehler et al.
patent: 4381202 (1983-04-01), Mori et al.
patent: 4447823 (1984-05-01), Maeguchi et al.
patent: 4489978 (1984-12-01), Sakurai
patent: 4592792 (1986-06-01), Corboy, Jr. et al.
patent: 4698316 (1987-10-01), Corboy, Jr. et al.
patent: 5608252 (1997-03-01), Nakato
M. Nandakumar, et al.,Shallow Trench Isolation for Advanced ULSI CMOS Technologies, IEDM, pp. 133-136 (1998).
Girard & Equitz LLP
National Semiconductor Corporation
Ngo Ngan V.
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