Low-speed subscriber extension type system

Details Low-speed subscriber extension type system Low-speed subscriber extension type system

2000-11-15

2004-12-14

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S463000, C370S538000, C370S543000, C370S545000

Reexamination Certificate

active

06831919

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to and claims all benefits accruing under 35 U.S.C. Section 119 from an application entitled “LOW-SPEED SUBSCRIBER EXTENSION TYPE SYSTEM” filed in the Korean Industrial Property Office on Nov. 15, 1999 and there duty assigned Serial No. 99-50537.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an asynchronous transfer mode (ATM) switching system. More particularly, the present invention relates to a system for extending the system capacity to accommodate more of the low-speed subscribers in an ATM switching system.
2. Description of the Related Art
The current trend in the ATM switching system demonstrates a decrease in the component size and fabrication cost per port but an increase in the bandwidth of a switch link. Some of the elements of the ATM switching system, such as the switch, subscriber device, controller and network synchronization device, are typically mounted on a single shelf. However, due to the physical limitation of a given single shelf, the number of slots allocated for accommodating subscribers is thus limited to 14 to 16. Moreover, due to the increase demand for more bandwidth in the switch link, 622 Mbps bandwidth is now typically used. Hence, a subscriber board of over DS3 (Digital Signal level Three) class can use the entire bandwidth available in the switch link. Thus, if the subscriber requires a low-speed transmission using the low-speed subscriber board, the bandwidth utilization efficiency of the switch link is inefficient.
With reference to
FIG. 1
, a simplified block diagram illustrating the capacity of low-speed subscribers in a general ATM switching system is depicted to show the above inefficiency of the bandwidth utilization. The conventional ATM switching system, as shown in
FIG. 1
, processes an ATM cell stream received through a switch link and transmits the processed ATM cell stream to low-speed subscriber links #0-#N via a line interface unit (LIU)
30
. Here, because of the physical limitation of the subscriber board (i.e., the board size is 413 mmx×315 mm), the maximum capacity or number of subscribers is limited within the range of 16 to 32 (i.e., N=31 in FIG.
1
). The subscriber capacity is limited by the physical size of the PBA (Physical Block Address). Yet, due to the demand for higher bandwidth and applications in the present state, the transfer rate of the switch link has increased dramatically. Presently, a transfer rate of 622 Mbps is typically used. However, when 32 E1 subscribers requiring a low-speed transmission are accommodated in the system with the bandwidth of 65.536 Mbps (32×2.048 Mbps), a waste of 556 Mbps in the bandwidth occurs as the maximum bandwidth of 622 Mbps is not fully utilized due to the design limitation in the shelf switching system.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a low-speed subscriber extension type system for extending the capacity of low-speed subscribers so as to increase the utilization efficiency of a switch link in an ATM switching system.
To achieve the above and other objects, there is provided a low-speed subscriber extension type system for extending the capacity of low-speed subscribers in an asynchronous transfer mode (ATM) switching system. In this system, a low-speed subscriber board interfaces with a switch link through a system backboard, receives a cell transmitted from the switch link, then multiplexes/demultiplexes the received cell through a UTOPIA interface after switch link and the ATM layer processing. A low-speed subscriber physical layer board transmits data, which is a physical layer processed in the low-speed subscriber board, to a low-speed subscriber and serializes the cell transmitted from the low-speed subscriber board into a clock and data before the transmission. A low-speed multiplexing/demultiplexing board recovers the clock and data from the serial data received from the low-speed subscriber physical layer board via a cable, converts the clock and data to parallel data in a word unit, transmits the parallel data to a corresponding low-speed extension board through a low-speed bus, reads cells received from a given low-speed extension board, multiplexes the read cells, and transmits the multiplexed cells to the low-speed subscriber physical layer board through a link processor. Each low-speed extension board exchanges a cell with the low-speed multiplexing/demultiplexing board through a low-speed bus, performs physical layer processing on the cell of the corresponding board, and transmits a received cell to the corresponding subscriber through the low-speed extension physical layer board.


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Utopia Level 1 Version 2.01 (af-phy-0017.000), ATM Forum, Mar. 21, 1994.*
Utopia Level 2 Version 1.0 (af-phy-oo30.000), ATM Forum, Jun. 1995.*
Publication ISSN 0285-4139—NEC Technical Journal, Apr. 23, 1995, vol. 48, No. 4, pp. 27-38.

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