Low speed serial bus protocol and circuitry

Details Low speed serial bus protocol and circuitry Low speed serial bus protocol and circuitry

1995-12-29

1998-10-06

Harvey, Jack B.

Multiplex communications

Wide area network

Packet switching

395290, 370438, G06F 1300

Patent

active

058190511

ABSTRACT:
A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.

REFERENCES:
patent: 4608700 (1986-08-01), Kirtley, Jr. et al.
patent: 4785396 (1988-11-01), Murphy et al.
patent: 5233350 (1993-08-01), Khim
patent: 5265093 (1993-11-01), Dissosway et al.
patent: 5319765 (1994-06-01), Kimura
patent: 5590292 (1996-12-01), Wooten et al.
Compaq Deskpro 386/20.TM. Technical Reference Guide, vol, I, Ch. 2, System Board, Keyboard Interface and Controller, pp. 2-86 to 2-100, 1987.
Technical Manual for the System/2 Mouse (date unknown).
Compaq Deskpro 386/20.TM. Technical Reference Guide, vol, II, Ch. 5, Keyboard, pp. 5-10 to 5-37, 1987.

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