Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-25
2001-11-06
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S342000, C257S365000
Reexamination Certificate
active
06313512
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to field effect transistors (FETs), and more specifically to radio frequency power amplifier FETs designed for minimum source inductance.
BACKGROUND OF THE INVENTION
In high frequency (e.g. microwave) applications, through wafer via holes are used for grounding purposes so as to effectively distribute the ground connections throughout the device. That is, through wafer vias operate to distribute as much as possible the ground signal connections throughout the whole device. However, in low frequency applications, (e.g. under 2.5 Ghz) such grounding typically occurs via bond wires which connect to the package of an IC chip. In designing field effect transistors (FETs) for applications where frequencies are low (e.g. <2.5 GHz) and through-wafer vias are not used due to cost reasons, manufacturers optimize the FET topology for minimum source inductance. An example of this type of prior art device is the Philips CGY2030 3 volt, 0.5 watt 1900 MHz radio frequency power amplifier shown in FIG.
1
.
This optimization results in a configuration where the source fingers
30
′ lead directly to the edge of the chip where bond wires connect the source fingers directly to ground without an on-chip bus, in an attempt to minimize source inductance. The gate fingers
40
′ are bussed and center-fed. The drain fingers
50
′ are also bussed together and cross over both the source and gate connections.
It is well known that drain lines and source lines carry large currents. Accordingly, handling these large currents requires relatively thick metallization layers. Unfortunately, thick metal traces cannot be patterned to very fine dimensions. Because of these large dimensions, making a bus connection that crosses over a thick metal requires a large space. These spaces and large connections end up determining the minimum gate finger spacing. In the prior art, the gate finger spacing is typically around 15-20 &mgr;m. As illustrated in the prior art
FIGS. 1 and 2
, the drain lines undesirably cross over both the source and gate fingers. That is, as shown in
FIG. 2
, the drain fingers
50
′ are coupled to the drain bus
80
′ so that the drain, gate, and source lines cross over one another within the active region
101
′ of the FET device. These crossover areas are illustrated as reference numeral
75
′ and
77
′. Accordingly, it is highly desirable to obtain a FET cell topology which eliminates crossover of the large current drain lines with the source and gate lines so as to reduce the gate finger spacing, as well as the overall size of the semiconductor device.
This invention eliminates the need to cross the drain lines over the source lines. By doing so, gate finger spacing no longer depends on design rules for thick metallization. This allows a much more compact FET layout which advantageously permits gate to gate spacing to be reduced by approximately 30% to 50% (8.6 to 12 &mgr;m) from the current gate to gate spacings.
SUMMARY OF THE INVENTION
A field effect transistor (FET) comprising a plurality of drain finger electrodes, source finger electrodes and gate finger electrodes disposed in an active region of a semiconductor substrate; a drain bus disposed outside the active region and electrically connecting the drain finger electrodes to each other; a gate bus disposed outside the active region and electrically connecting the gate finger electrodes to each other; and a source bus disposed outside the active region and electrically connecting the source finger electrodes to each other; wherein the drain fingers are electrically connected to each other via the drain bus without crossing over the source or gate fingers.
There is also disclosed a method of forming a field effect transistor comprising the steps of disposing a doped layer onto the top surface of the substrate, and wherein the step of forming a plurality of drain finger electrodes, source finger electrodes and gate finger electrodes within said active region comprises disposing an ohmic metal layer over a portion of the doped layer; and a first metal layer onto the ohmic metal layer to form the drain finger electrodes; disposing a gate metal layer over another portion of the doped layer; and a first metal layer onto the gate metal layer to form the gate finger electrodes; and disposing an ohmic metal layer over a third portion of the doped layer; and a first metal layer onto the ohmic metal layer to form the source finger electrodes.
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Abbott Victor G.
Schmitz Norbert A.
Chaudhuri Olik
Duane, Morris & Hecksch
Ha Nathan W.
Plevy Arthur L.
Tyco Electronics Logistics AG
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