Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1996-02-28
1998-06-23
Ray, Gopal C.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 28, G06F 126
Patent
active
057713898
ABSTRACT:
A low slew rate buffer is described. The low slew rate buffer comprises an output pad. A first transistor is coupled to the output pad. The first transistor drives the output pad to a first state when the first transistor is switched on. A second transistor is coupled to the output pad. The second transistor drives the output pad to a second state when the second transistor is switched on. A predriving unit is coupled to the first and second transistors. The predriving unit switches the first transistor off and supplies a staged biasing voltage which gradually turns on the second transistor.
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Intel Corporation
Ray Gopal C.
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