Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-08-01
2001-09-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000, C326S038000, C326S047000
Reexamination Certificate
active
06292020
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to programmable routing resources for programmable logic devices.
BACKGROUND
Programmable logic devices (PLDs) are a well-known type of integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), can implement thousands of gates of logic on a single integrated circuit. PLDs, including FPGAs, are becoming ever more popular, largely because they require less time to implement than semi-custom and custom integrated circuits.
FIG. 1
(prior art) depicts a conventional FPGA
100
. As is typical, FPGA
100
includes an array of configurable logic blocks (CLBs)
105
that are programmably connected to each other and to programmable input/output blocks (IOBs)
110
. CLBs
105
include memory arrays that can be configured either as look-up tables (LUTs) that perform specified logic functions or as random-access memory (RAM). Some modern FPGAs also include embedded blocks of RAM
115
optimized for memory applications. Configuration data loaded into internal configuration memory cells (not shown) define the operation of the FPGA by determining how the CLBs, interconnections, block RAM, and IOBs are configured. FPGA
100
may be, for example, a Virtex™ FPGA available from Xilinx, Inc., of San Jose, Calif. For a more detailed description of a Virtex™ FPGA, see “Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays,” advance product specification, DS025 (v
1
.
0
) Mar. 23, 2000, pages 1-19, which is available from Xilinx, Inc., and is incorporated herein by reference.
FIG. 2
(prior art) depicts another view of FPGA
100
of
FIG. 1
, like-numbered elements being the same. A majority of CLBs
105
and IOBs
110
are omitted for simplicity. A pair of CLBs
105
A and
105
B represents two signal sources, each intended to drive a shared signal to a plurality of IOBs
110
. Referring first to the left-hand side of FPGA
100
, CLB
105
A connects to a vertical interconnect line
200
via a buffer
205
and a programmable interconnect point (PIP)
210
A. PIP
210
A is one of a collection of conventional PIPs used to programmably connect various horizontal and vertical conductors to define desired signal paths. For illustrative purposes, programmed PIPs and the associated signal paths are depicted in
FIG. 2
using relatively wide lines.
FPGA
100
is configured such that CLB
105
A provides a shared signal S to a series of IOBs
110
, the series collectively designated
215
. Such configurations are typical when implementing communication channels (e.g., input or output busses) in which a collection of IOBs
110
share common signals, such as clock, clock-enable, write-enable, output-enable, preset and clear signals, to name just a few. In this specification, the IOBs connected to CLB
105
A or CLB
105
B are designated as “
”, and the unused IOBs are empty boxes.
The common signal S from CLB
105
A traverses different lengths of interconnect lines, depending upon the destination. Consequently, signal S arrives at the various IOBs
110
within series
215
at slightly different times. This difference, conventionally known as “skew,” can be a significant problem when attempting to synchronously send or receive relatively fast signals in parallel. For example, it can be very difficult to control a number of IOBs
110
in parallel, as is required to implement a control channel. This problem is exacerbated when the control signal S has both minimum and maximum delay constraints.
In general, the greater the number and separation of signal destinations that must be synchronized, the greater the skew problem. This is particularly true when signals must be routed to IOBs along more than one edge, a situation illustrated on the right-hand side of FIG.
2
. In that example, the number of IOBs
110
along the right-hand edge is insufficient to implement a desired synchronous communication channel. Thus, two IOBs
110
from the upper edge of FPGA
100
are joined with a collection of IOBs
110
along the right-hand edge. Unfortunately, wrapping the synchronized signal from signal source
105
B around a corner using the conventional interconnect scheme of
FIG. 2
exacerbates the skew problem by requiring the inclusion of a group of additional PIPs and interconnect conductors
220
. The resulting additional skew can cause FPGA
100
to fail to meet a required timing specification, possibly leading to timing errors. There is therefore a need for improved programmable routing resources capable of distributing low-skew signals along more than one edge of a programmable logic device.
SUMMARY
The present invention is directed to an improved programmable routing resource capable of distributing low-skew signals along more than one edge of a programmable logic device (PLD). PLDs conventionally include a first group of IOBs arranged along a first edge of the PLD and a second group of IOBs arranged along a second edge of the PLD. A PLD in accordance with the invention conveys shared signals to both groups of IOBs from an area near the corner of the PLD defined by the meeting of the first and second edges.
In one embodiment, the first group of IOBs connects to the signal source via a first conductive segment (e.g., a metal line) disposed in parallel with the first edge, and the second group of IOBs connects to the signal source via a second conductive segment disposed in parallel with the second edge. An interconnect segment extends from the signal source toward the area near the corner defined by the first and second edges. In this context, an area is “near” a given corner if the area is physically closer to the given corner than to the remaining corners. A pair of PIPS in the corner area selectively connects the interconnect segment to one or both of the first and second conductive segments. Distributing signals shared by the first and second groups of IOBs from a point between the groups minimizes skew between the various IOBs.
Each of the first and second conductive segments extends only part-way along the length of the corresponding edge. Each edge therefore includes an additional conductive segment that extends along the remaining portion. The additional segment allows shared signals to be provided to those IOBs not available to the first and second conductive segments. These additional segments can be connected to signal sources via an interconnect line that extends to an area of the PLD near a second corner adjacent to the first corner. Shared signals are thus conveyed along the edges of the PLD from the corners, an arrangement that reduces the amount of skew between IOBs on different edges. IOBs and interconnect resources similar to those described above are laid out along the remaining two edges of the PLD.
IOBs often require more than one synchronous signal. A PLD in accordance with one embodiment of the invention therefore includes a number of signal-distribution networks similar to the one described above.
This summary does not purport to define the invention. The invention is defined by the claims.
REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 5296759 (1994-03-01), Sutherland et al.
patent: 5298805 (1994-03-01), Garverick et al.
patent: 5712579 (1998-01-01), Doung et al.
patent: 6064225 (2000-05-01), Andrews et al.
Xilinx Advance Product Specification, “Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays”, DS025 (v1.0) Mar. 23, 2000, pp. 1-19.
Behiel Arthur J.
Tan Vibol
Tokar Michael
Xilinx , Inc.
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