Low skew multiplexer network and programmable array clock/reset

Details Low skew multiplexer network and programmable array clock/reset Low skew multiplexer network and programmable array clock/reset

1996-09-06

1998-02-10

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326101, 327295, H03K 1900

Patent

active

057173460

ABSTRACT:
A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

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