Low skew differential receiver with disable feature

Details Low skew differential receiver with disable feature Low skew differential receiver with disable feature

1998-08-27

2000-08-15

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326 33, 326 58, 326 86, 327112, 327262, 327563, H03K 190185, H03K 19003

Patent

active

061042099

ABSTRACT:
A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

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