Low scratch density chemical mechanical planarization process

Details Low scratch density chemical mechanical planarization process Low scratch density chemical mechanical planarization process

1997-06-13

2000-08-29

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438692, 438697, H01L 21304

Patent

active

061108200

ABSTRACT:
A CMP process using two or more stages wherein each stage has a different polishing rate. The CMP process is characterized by a final stage that is longer in duration than performed in the prior art. In a particular example the final stage is approximately equal in duration to the initial stage. Alternatively, the final stage is performed so as to polish to depth sufficient to remove scratches created at the inititiation of the final polishing. Scratches initiated at the beginning of the final stage of polishing are removed by the extended length of time of the later stage of polishing.

REFERENCES:
patent: 3841031 (1974-10-01), Walsh
patent: 4070797 (1978-01-01), Griesshammer et al.
patent: 4184908 (1980-01-01), Lackner et al.
patent: 4193226 (1980-03-01), Gill, Jr. et al.
patent: 4680893 (1987-07-01), Cronkhite et al.
patent: 4811522 (1989-03-01), Gill, Jr.
patent: 4968381 (1990-11-01), Prigge et al.
patent: 5096854 (1992-03-01), Saito et al.
patent: 5142828 (1992-09-01), Curry, II
patent: 5244534 (1993-09-01), Yu et al.
patent: 5320706 (1994-06-01), Blackwell
patent: 5328553 (1994-07-01), Poon
patent: 5395801 (1995-03-01), Doan et al.
patent: 5429711 (1995-07-01), Watanabe et al.
patent: 5449314 (1995-09-01), Meike et al.
patent: 5491113 (1996-02-01), Marota
patent: 5502007 (1996-03-01), Maruse
patent: 5514245 (1996-05-01), Doan et al.
Wolf, Stanley, "Silicon Processing for the VLSI Era", vol. 1, pp. 23-25.
Vincent Y. Pickhardt et al., "Chemomechanical Polishing of CdS," J. Electrochem. Soc.: Solid-State Science and Technology, Aug. 1974.
T. Katada et al., "Hall Effect, Schottky Barrier Capacitance, and Photoluminescence Spectra Measurements for GaAs Epitaxial Layer and Their Correlation," Dept. of Electrical Engineering, The University of Tokyo, Japan.
Rodel, "Polishing with napped poromerics: an overview," Surfacetech Review, vol. 1, Issue 1, Dec. 1986.
Rodel, "A "Sound"Reason for a Precesion Surface," Surfacetech Review, vol. 1, Issue 6, May 1989.
W.L.C.M. Heyboer et al., "Chemomechanical Silicon Polishing," J. Electrochem. Soc., vol. 138, No. 3, Mar. 1991.
William J. Patrick et al., "Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections," SP 04474, J. Electrochem. Soc., vol. 138, No. 6, Jun. 1991.
C. Yu et al., "Submicron Aluminum Plug Process Utilizing High Temperature Sputtering and Chemical Mechanical Polishing," Conference Proceedings ULSI-VII, 1992.

Affiliated with

Also associated with

Rating

Low scratch density chemical mechanical planarization process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low scratch density chemical mechanical planarization process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low scratch density chemical mechanical planarization process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1249398