Low rise/fall skewed input buffer compensating process...

Details Low rise/fall skewed input buffer compensating process... Low rise/fall skewed input buffer compensating process...

2007-03-06

2007-03-06

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S087000, C327S112000

Reexamination Certificate

active

10716079

ABSTRACT:
Buffer circuits and techniques that reduce skew between rising and falling times of output data as process conditions vary are provided. One or more process-dependent current sources may be utilized to compensate for process variations by supplementing the current drive of transistors used to precharge (PMOS) or discharge (NMOS) an output node of a secondary (e.g., inverter) stage of the buffer circuit.

REFERENCES:
patent: 5847581 (1998-12-01), Allen
patent: 6492836 (2002-12-01), Kiehl

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