Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-05
2001-10-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S628000, C438S629000, C438S643000, C438S644000, C438S648000, C438S650000, C438S653000, C438S654000, C438S656000, C438S659000, C438S685000, C438S686000, C438S687000
Reexamination Certificate
active
06297146
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to barrier materials used in semiconductor processing.
BACKGROUND ART
In the manufacture of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a “dual damascene” technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical “via” at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and an optional thin adhesion layer is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer improve the formation of subsequently deposited conductive material and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices. A- first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diff-uses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), or titanium nitride (TiN) are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as titanium, is first deposited on the dielectrics or vias to ensure good adhesion and good electrical contact of subsequently deposited “barrier” (also called “seed”) layers to underlying doped regions and/or conductive channels. Adhesion/barrier layer stacks formed of adhesion/barrier materials such as tantalum/tantalum nitride (Ta/TaN) and titanium/titanium nitride (Ti/TiN) have been found to be useful as adhesion/barrier material combination for copper interconnects.
The “barrier effectiveness” of a barrier layer with respect to a conductive material is its ability to prevent diffusion of the conductive material. The barrier effectiveness of a barrier layer is determined in part by its thickness, including the thickness uniformity, and its quality, including the number and sizes of defects such as pinholes which form on deposition. To resist copper diffusion, it is found that a minimum barrier layer thickness of 5 nm is currently required with the currents currently in use. However, to minimize the electrical resistance due to the barrier layer, it is desirable to maintain a thin barrier layer. Therefore, it is also currently desirable to keep the barrier layer thickness close to about 5 nm.
However, as semiconductors shrink in size, the barrier layer thickness must also shrink. A solution, which would permit thinner barrier layers with a reduction in the electrical resistance of the barrier layers without a decrease in their barrier effectiveness has long been sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and diffusiveness through dielectrics, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor with a barrier layer, having a Group VIII B element combined with a Group V B or VI B element, which has increased barrier effectiveness and lower resistivity.
The present invention provides a semiconductor with a barrier layer, having a Group VIII B element alloyed with a small amount of a group V B or VI B element for semiconductors having conductive materials in Group I B, which has increased barrier effectiveness and lower resistivity.
The present invention provides a semiconductor with an barrier layer, having a substantially pure Group VIII B adhesion layer for a Group VIII B element alloyed with a small amount of a Group V B or VI B element for semiconductors having conductive materials in Group I B, which has increased barrier effectiveness and lower resistivity.
The present invention provides a semiconductor with a barrier layer, having cobalt (Co), nickel (Ni), or palladium (Pd) alloyed with tantalum (Ta), molybdenum (Mo), or tungsten (W), which has increased barrier effectiveness and lower resistivity.
The present invention provides a semiconductor with a barrier layer, having cobalt (Co), nickel (Ni), or palladium (Pd) alloyed with between about 0.2% and 4% tantalum (Ta), molybdenum (Mo), or tungsten (W) for semiconductors having conductive materials of copper (Cu), silver (Ag), or gold (Au), which has increased barrier effectiveness and lower resistivity.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5695810 (1997-12-01), Dubin et al.
patent: 6153935 (2000-11-01), Edelstein et al.
patent: 6156644 (2000-12-01), Ko
Advanced Micro Devices , Inc.
Gurley Lynne
Ishimaru Mikio
Niebling John F.
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