Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-09
2003-09-16
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S643000, C438S644000, C438S687000, C438S763000
Reexamination Certificate
active
06620724
ABSTRACT:
BACKGROUND OF THE INVENTION
Semiconductor devices are employed in many types of equipment to perform a wide variety of applications. An important type of semiconductor device for use in the memory field is known as dynamic random access memory (DRAM). DRAM is extensively used for memory in computers. A basic DRAM cell may include a capacitor and a transistor formed in a semiconductor substrate. The capacitor stores a charge representing data. The transistor allows the data to be refreshed, read from, or written to the capacitor. By reducing the surface area of the capacitor or the transistor, more DRAM cells can fit onto a chip. The increase in the amount of DRAM cells results in greater memory capacity for the chip.
One method of minimizing the surface area of a DRAM cell is to vertically construct the components (i.e., where a semiconductor device includes components formed at several or more layers thereof). One way to accomplish such vertical construction may involve forming a trench in a semiconductor substrate. For example, a dielectric film may be deposited over the sides of the trench. Then, polysilicon may be deposited on the dielectric film, acting as one of the electrodes of the capacitor. A recess may be created in the polysilicon by removing a portion of the polysilicon through an etching process. Layers of conductive, semiconductive and/or insulating material can then be deposited in the recessed area of the polysilicon. The steps of etching the polysilicon and depositing new material can be repeated until the desired component is formed.
As the surface area of a memory cell is made smaller, and higher DRAM density is achieved, the trench area in which capacitors are formed may be reduced. Doped silicon (Si) and other semiconductor materials (i.e., “fill material”) are often filled into the trench and become part of the capacitor. For example, a memory cell fabricated as part of a 4 Mbyte DRAM chip may have a trench area of about 11.3 &mgr;M
2
. A memory cell fabricated as part of a 256 Mbyte DRAM chip may have a trench area of about 0.6 &mgr;m
2
. Similarly, a memory cell fabricated for use in a 1 Gbyte DRAM chip may have a trench area of about 0.32 &mgr;m
2
. Thus, the area of the trench typically, but not always, decreases as the memory capacity of the DRAM chip increases.
In order to compensate for the reduced surface area of a DRAM cell, trenches may be formed relatively deep into the substrate, for example between 4-8 &mgr;m below the substrate surface. This will permit the total area of the trench to remain the same, or even increase, when compared to a shallower but wider trench.
Deeper trenches are typically said to have a high aspect ratio. The “aspect ratio” is the ratio of the depth of a trench compared to the width of the opening at the top of the trench. For example, memory cells fabricated as part of a 256 Mbyte DRAM chip may include trench capacitors having an aspect ratio of between 10:1 and 20:1. This means that the depth of the trench walls is between 10 and 20 times greater than the width of the trench opening. In higher density DRAM chips, such as chips of 1 Gbyte or more, a typical trench aspect ratio may be on the order of 40:1 to 60:1 or higher. In such high aspect ratio situations, the trenches are typically very narrow. The very narrow trenches impact not only the thickness of the fill material of the capacitor, but also how the fill material is formed in the trench.
Capacitance and resistivity are important parameters that affect memory cell operation. For instance, the capacitance of the memory cell may need to remain above a certain level in order for the cell to store charge effectively. In particular, the cell may need to maintain a capacitance on the order of 25 fF. If the capacitance falls significantly below this level, the cell may discharge too rapidly and the data stored by the cell can be lost.
Resistivity needs to be as low as possible in order to effectively charge the capacitor. Preferably, the resistivity is below about 5,000 &mgr;&OHgr;·cm. In low aspect ratio trenches, fill material layers having about 100 nm thickness could be formed on the dielectric film, commonly known as a node dielectric, which lines the trench sidewalls while maintaining the resistivity of about 5,000 &mgr;&OHgr;·cm. However, the high aspect ratios of high-density DRAM designs require much thinner fill layers having a lower resistivity level.
Increasing the dopant concentration of the fill material acts to lower resistivity. A method of doping Si is to apply a layer of Si to the node dielectric lining the trench sidewalls, followed by a layer of dopant over of the Si. The dopant can be diffused into the Si by heating, or annealing, the two layers, for instance, in a later step in the process of forming an electrode the DRAM memory cell. One problem with this layering scheme in high aspect ratio trenches is the necessity of forming thin layers of material on the trench sidewalls while maintaining an adequate level of resistivity. Therefore, a need exists for improved capacitor fill material having narrow thickness. A need also exists for improved methods of forming the fill material with a high concentration of uniformly distributed dopant therein.
SUMMARY OF THE INVENTION
The present invention provides a fill material having a resistivity suitable for use in a capacitor. In one embodiment, a semiconductor device includes a semiconductor substrate, a transistor, and a capacitor formed in the substrate. The capacitor is electrically connected to the transistor. The capacitor is formed in a trench defined by sidewalls having a depth and a top opening having a width. A dielectric material lines a portion of the sidewalls. A layer of fill material is arranged on the dielectric material. The fill material includes a semiconductor base material and a dopant, and has a resistivity below 5,000 &mgr;&OHgr;·cm.
The depth of the sidewalls relative to the width of the top opening defines an aspect ratio of the trench. In one preferred embodiment, the aspect ratio is at least 20:1. More preferably, the depth of the sidewalls is between 4 to 8 &mgr;m and the aspect ratio is between 40:1 and 60:1.
In another preferred embodiment, the dopant may be selected from the group consisting of As, Sb and P. Similarly, the base material may be selected from the group of Si and SiGe. The dopant concentration is preferably at least 1×10
17
.
In accordance with another aspect of the present invention, a method of fabricating a semiconductor device is provided. The method includes forming a trench in a semiconductor substrate. The trench includes sidewalls defining a trench depth and a top opening defining a trench width. The sidewalls may be substantially covered with a dielectric material. A fill material having a resistivity below 5,000 &mgr;&OHgr;·cm is deposited on the dielectric material. Deposition is preferably performed by flowing a first gas and a second gas together over the trench at a selected temperature and pressure. The first gas includes a base material and the second gas includes a dopant. Flowing the first and second gasses together facilitates in situ doping of the base material.
In one preferred embodiment, the selected temperature is between 400° C. and 700° C. More preferably, the selected temperature is between 500° C. and 600° C. It is also preferable for the selected pressure is between 100 Torr and 1000 Torr.
The method may further comprise applying a relatively low temperature proximate to a top surface of the semiconductor substrate and a relatively high temperature proximate to a bottom surface of the semiconductor substrate. The temperature difference between the top and bottom surfaces may reduce bread loafing and to improve conformality.
In a preferred embodiment, the base material is Si, and the first gas is selected from the group consisting of SiH
4
, Si
2
H
6
, TCS, DCS and HDS.
In another preferred method, the fill material is formed by depositing a base layer on the dielectric material. The base layer is preferably less than 50 nm
Goldbach Matthias
Hauf Manfred
Jammy Rajarao
McStay Irene
Rousseau Jean-Marc
Infineon - Technologies AG
Lebentritt Michael S.
Lerner David Littenberg Krumholz & Mentlik LLP
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