Low resistance semiconductor process and structures

Details Low resistance semiconductor process and structures Low resistance semiconductor process and structures

2005-12-20

2005-12-20

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S343000, C257S345000

Reexamination Certificate

active

06977418

ABSTRACT:
A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

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