Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-09-03
2002-11-26
Lee, Eddie (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S586000, C438S664000
Reexamination Certificate
active
06486060
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor assembly, and more particularly to a process for forming conductive structures having enhanced conductivity, and the in-process structure resulting from the process.
BACKGROUND OF THE INVENTION
Structures such as polycrystalline silicon (poly) plugs, interconnects, and transistor gates are commonly formed during the manufacture of semiconductor devices such as microprocessors, memory devices, and logic devices. To manufacture a plug, for example, a masked dielectric layer is formed over an underlying substrate assembly and an etch is completed to form a hole in the dielectric which exposes the underlying structure in the area where contact is to be made. A blanket poly layer is deposited over the dielectric layer which fills the hole in the dielectric layer and contacts the underlying structure. The poly is then removed from a planar surface of the dielectric, typically using a chemical mechanical polishing (CMP) process which leaves the plug formed within the dielectric layer. Interconnects and gates are typically formed by depositing a blanket layer of poly over a semiconductor substrate assembly, then masking and etching the layer.
As the sizes of the plugs and line widths decrease with improving manufacturing technology, the doped poly structure may provide excessive resistance and insufficient conductance. To reduce the resistance of a structure, a silicide layer is often formed underneath the plug or over the top of the plug, gate or interconnect. To form the silicide layer to enhance plug conductivity the silicide layer can be formed before formation of the plug. A titanium chemical vapor deposition (CVD) process results in titanium reacting with the exposed silicon wafer to form titanium silicide. An unreacted titanium metal layer will also form over any exposed dielectric layer which is then stripped. After stripping the unreacted titanium, the poly plugs are formed over the silicide layer as described above.
A silicide layer can also be formed over the plug, transistor gate or other interconnect after forming the blanket poly layer which forms the gate or interconnect. During a titanium CVD process similar to that described above for forming silicide under the plug, the titanium reacts with the polysilicon to form silicide on top of the poly layer, then the poly is masked and etched to define the line or plug.
U.S. Pat. No. 5,381,302 by Sandhu et al. and U.S. Pat. No. 5,198,384 by Dennison, each assigned to Micron Technology, Inc. and incorporated herein by reference in their entirety, describe a process for forming a silicide layer over a poly plug.
While the silicide layer interposed between the silicon wafer and the poly plug provides decreased resistance and increased conductance it can also provide a path for leakage between an adjacent transistor channel region and an active area, thereby increasing junction leakage. A process and structure which provides improved conductance and reduced resistance and which does not increase junction leakage would be desirable. It would be further desirable to provide a plug having a maximized amount of silicide formed thereon.
SUMMARY OF THE INVENTION
The present invention provides a new process and structure having fewer problems associated with the formation of silicided polycrystalline silicon plugs, particularly problems resulting in excessive transistor junction leakage. In accordance with one embodiment of the invention, a semiconductor substrate assembly is provided which comprises a semiconductor wafer, a plurality of transistor gates, and a plurality of conductive plugs which contact the wafer. A silicide layer is formed which simultaneously forms to contact the plurality of gates and the plurality of plugs. In another embodiment, a plug is formed which comprises silicide on the sidewalls, thereby maximizing the amount of the desirable silicide to minimize resistance.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
REFERENCES:
patent: 5198384 (1993-03-01), Dennison et al.
patent: 5381302 (1995-01-01), Sandhu et al.
patent: 5422296 (1995-06-01), Lage
patent: 5536683 (1996-07-01), Lin et al.
patent: 5854127 (1998-12-01), Pan
patent: 5899742 (1999-05-01), Sun
patent: 5998257 (1999-12-01), Lane et al.
patent: 6013547 (2000-01-01), Liaw
patent: 6096638 (2000-08-01), Matsubara
patent: 6175146 (2001-01-01), Lane et al.
patent: 6261899 (2001-07-01), Lane et al.
Hermes Michael J.
Parekh Kunal R.
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