Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-22
2001-02-27
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S243000, C438S386000
Reexamination Certificate
active
06194755
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacture and design of trench capacitors for integrated circuit devices, especially capacitors for use in dynamic random access memory (DRAM) cells and advanced memory devices containing the same.
BACKGROUND OF THE INVENTION
Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) cell comprises a plurality of memory cells which are used to store large quantities of information. Each memory cell typically includes a capacitor for storing electric charge and a field effect transistor (FET) for opening and closing charge and discharge passages of the capacitor. The number of cells (and corresponding bits of memory capacity) of DRAM integrated circuit chips has been increasing by approximately 4×every three years; this has been achieved by reducing memory cell size. Unfortunately, the smaller cell size also results in less area to fabricate the capacitor.
Moreover, as DRAM cell dimensions are scaled down with each successive generation, the cross-sectional area of the deep trench storage capacitor diminishes inversely with the square of the ground rule, while the trench depth has remained approximately constant. This change in trench geometry results in a large increase in the series resistance contributed by the polysilicon electrode contained in the deep trench. The increased resistance in turn may adversely limit the speed at which the corresponding memory cell can be accessed.
One approach to decrease the series resistance of DRAM trench capacitors is to increase the doping concentration of the deep trench polysilicon. This approach however only provides a marginal reduction in series resistance and thus has limited applicability in fabricating DRAM cells of decreased dimension.
Thus, there is a continued need for new manufacturing processes and/or designs which more effectively address the problem of series resistance in the context of trench capacitors and devices incorporating such capacitors (e.g., DRAM chips).
SUMMARY OF THE INVENTION
The present invention provides trench capacitor structures and methods of fabricating trench capacitors wherein the distributed series resistance of the deep trench electrode is substantially reduced for a given trench geometry.
The present invention provides trench capacitor structures and methods of fabricating trench capacitors wherein the series capacitance of the deep trench electrode is substantially increased for a given trench geometry.
A still further object of the present invention is to provide a trench capacitor structure which can be used conventional DRAM and in advanced memory cell devices.
In one aspect, the invention encompasses a process wherein a refractory metal salicide material is formed in a lower trench region of a trench capacitor. The trench is preferably bottle-shaped. The process of the invention preferably comprises:
(a) filling a storage trench in a semiconductor substrate, the trench having a narrow upper region and a broad lower region, with a layer of polysilicon leaving a void in the broad lower region of the trench;
(b) planarizing the structure provided in step (a);
(c) recessing the layer of polysilicon in the narrow upper region of the trench so as to expose the void in the broad lower region of the trench;
(d) forming a conformal refractory metal layer over said bottle-shaped storage trench including in said narrow upper region and said broad lower region;
(e) forming a refractory metal salicide layer in said broad lower region of said trench;
etching said conformal refractory metal layer from said narrow upper region of said trench;
(g) filling said trench with polysilicon; and
(h) planarizing the structure provided in step (g).
Step (e) is preferably conducted using a selective reaction which is capable of converting the refractory metal formed in the broad lower region of said trench to a refractory metal salicide having low-resistance.
Another aspect of the present invention relates to a trench capacitor structure having a salicide present in the trench. The capacitor structure of the present invention is preferably useful as a storage capacitor in a DRAM memory cell. The capacitor structure of the invention preferably comprises a storage trench having a narrow upper region and a broad lower region, wherein the broad lower region comprises an outer layer of polysilicon over which is formed a refractory metal salicide layer and a polysilicon inner layer. The storage trench is preferably bottle-shaped.
A further aspect of the present invention is directed to advanced memory cell devices which contain at least the DRAM cell capacitor structure of the present invention therein as one of its components.
These and other aspects of the invention are described in further detail below.
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patent: 5395786 (1995-03-01), Hsu et al.
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patent: 5943581 (1999-08-01), Lu et al.
patent: 63-62371 (1988-03-01), None
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patent: 4-287366 (1992-10-01), None
Process for Trench Planarization, IBM Technical Disclosure Bulletin, vol. 29, No. 3, pp. 1240-1242 (Aug. 1986).
Isolation Merged Stacked Dynamic Random-Access Memory Cell, IBM Technical Disclosure Bulletin, vol. 31, No. 7, pp. 39-42 (Dec. 1988).
Badih El-Kareh, IBM Corporation, Fundamentals of Semiconductor Processing Technologies, Kluwar Academic Publishers, pp. 534-546.
Gambino Jeffrey P.
Gruening Ulrike
Mandelman Jack A.
Radens Carl J.
Capella, Esq. Steven
Diaz José R.
International Business Machines - Corporation
Saadat Mahshid
Scully Scott Murphy & Presser
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