Low resistance plate line bus architecture

Details Low resistance plate line bus architecture Low resistance plate line bus architecture

2006-04-24

2008-10-28

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S063000, C365S189090, C365S230030

Reexamination Certificate

active

07443708

ABSTRACT:
An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

REFERENCES:
patent: 5671174 (1997-09-01), Koike et al.
patent: 6473331 (2002-10-01), Takashima
patent: 6847539 (2005-01-01), Aoki
patent: 6934179 (2005-08-01), Shuto
patent: 7269048 (2007-09-01), Takashima

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