Low resistance interconnect for a semiconductor device and...

Details Low resistance interconnect for a semiconductor device and... Low resistance interconnect for a semiconductor device and...

1999-11-01

2001-06-19

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S751000, C257S763000, C257S764000, C257S765000, C257S770000

Reexamination Certificate

active

06249056

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to interconnections having a multilevel metal structure and process for fabricating the structure.
BACKGROUND OF THE INVENTION
The density of semiconductor devices continues to increase due to decreasing semiconductor feature sizes. In order to minimize chip size, the techniques related to manufacturing process, device physics, and reliability in the field of sub-micron semiconductor devices are continually being challenged, developed, and refined.
The metallization process provides interconnections between contacts within semiconductor devices and between devices and conductive pads. To make electrical connections in smaller and more complex chips, multilevel metal interconnects are formed in the semiconductor process. The metal interconnect may be composed of Al, Ti, Cu, W, or other suitable conductive material or combination. A recess such as hole or via is bored through a dielectric covering a first level layer of metal, or a second level layer of metal. The recess is filled with a conductive material (i.e. Al, Ti, Cu, W). The conductive material in the via provides an electrical connection between the first metal layer and the second metal layer or between any two metal layers.
In VLSI multilevel metallization structures, reliability problems of the via can be associated with the aspect ratio of the via, step conditions of the metallization process and materials used in fabricating the via.
FIG. 1
illustrates a step of a conventional interconnection process etching through a dielectric layer
16
into capping layer
14
for forming a via to the conductive layer
12
, which is formed on semiconductor layer
10
having a barrier layer (not shown). Unfortunately it is difficult to precisely etch the capping layer
14
through the dielectric layer
16
without etching the underlaying conductive layer
12
. When overetching the conductive layer (i.e. Al)
12
, the chemical etchant (i.e. CF
4
, CBF
3
) reacts with the aluminum layer
12
and produces an AlF series polymer
20
on the walls of the via or the bottom of the via, which has a higher electrical resistance than the aluminum layer
12
. The high contact resistance of polymer
20
may induce electrical failure of the via contact. Overetching the aluminum
12
also damages the aluminum layer, which may weaken the electromigration characteristics of the aluminum layer
12
.
FIG. 2
illustrates another conventional interconnection process directed to solving the problem of producing the high resistivity AlF series polymer. The conventional process includes the steps of forming an aluminum layer
32
on a barrier layer of a surface of the semiconductor (not shown); forming an intermetallic layer
34
(i.e. titanium aluminum TiAl
3
) by heating or annealing a titanium layer to react with the underlying aluminum layer
32
; forming a titanium nitride layer
36
on the intermetallic layer
34
; depositing an interlevel dielectric layer
38
(i.e. silicon dioxide SiO
2
) on the titanium nitride layer
36
; etching a portion of the dielectric layer
38
; and depositing a titanium layer
42
and a titanium nitride layer
44
as a glue layer or an antireflective coating layer (ARC layer) on the dielectric layer
38
and the whole surface of the via
40
(see for example U.S. Pat. No. 5,360,995). The intermetallic layer
34
may protect the overetching of the aluminum layer
32
because the intermetallic layer
34
can be an overetching stop layer of the aluminum layer. But the intermetallic layer
34
unfortunately has a high resistivity, which is an undesirable characteristic in a semiconductor device. Despite providing improvements in via
40
, the via contact still has problems due to resistivity of the contact and electromigration characteristics of the metal line and via.
SUMMARY OF THE INVENTION
The present invention is intended to solve the problems, and it is an object of the invention to simplify the process and improve the reliability of the via.
It is another object of the invention to provide the reduction of the via resistance in order to improve electromigration characteristics of the via.
It is an additional object of the invention to provide a reduction of the via process steps for manufacturing semiconductor devices.
According to an aspect of the invention, a semiconductor device has a capping layer and a glue layer between a conductive via plug and a conductive layer in order to prevent damage to the conductive layer and preserve the electromigration characteristics of the conductive layer. The glue layer (i.e. titanium nitride TiN) is provided to prevent the production of undesired material during the via etching process. The capping layer is provided to reduce the contact resistance of the via.


REFERENCES:
patent: 5635763 (1997-06-01), Inoue et al.

Affiliated with

Also associated with

Rating

Low resistance interconnect for a semiconductor device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low resistance interconnect for a semiconductor device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low resistance interconnect for a semiconductor device and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2520563