Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-22
2001-05-22
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S750000, C257S360000, C438S197000, C438S592000
Reexamination Certificate
active
06236094
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor devices. More particularly, the invention relates to a process for forming low resistance gate electrodes in semiconductor devices.
Typical silicon MOS devices have a polysilicon gate and silicon dioxide as an insulator. The polysilicon/silicon dioxide system is well known in the art and can be controlled. However, the polysilicon can have a high resistance (greater than about 20 &OHgr;/[ ]) and this resistance can limit the speed of the circuits fabricated with this system. Previous approaches to lowering the resistance of a polysilicon gate electrode have included the formation of a silicide region on the top of an MOS transistor's polysilicon (“poly”) gate electrode. Silicide layers are conventionally formed by a variety of processes, including: (1) depositing a lower resistance conductor, such as a silicide (for example tungsten silicide (WSi
2
), titanium silicide (TiSi
2
), and cobalt silicide (CoSi
2
)) on the polysilicon that is mechanically defined with the polysilicon, or (2) depositing a refractory metal and forming a silicide on the polysilicon. The silicide has a lower resistance than the underlying doped silicon or poly. As a result, signal propagation through the poly gate electrode is enhanced.
FIGS. 1A through 1E
illustrate a conventional silicide process on a portion of a semiconductor wafer, such as is also described in S. Wolf, et al.,
Silicon Processing for the VLSI Era,
vol.1, 397-399 (Lattice Press, 1986), which is incorporated by reference herein for all purposes. In
FIG. 1A
, a portion of a semiconductor wafer
100
having a semiconductor substrate
101
(typically monocrystalline silicon) is shown. The substrate
101
has gate oxide
102
and poly
104
layers generated successively on its upper surface
106
. The gate oxide
102
and poly
104
layers are created in ways well known to those of skill in the art. For example, the gate oxide may be silicon dioxide (SiO
2
) generated by thermal oxidation of surface
106
of the silicon substrate
101
, and the poly
104
may be deposited on the gate oxide
102
by chemical vapor deposition.
FIG. 1B
shows the wafer
100
after the poly layer
104
has been patterned and etched to form a gate electrode
108
according to methods well known in the art (e.g., photolithography and plasma etching).
At this point, an ion implantation may be performed to form at least a portion of the source and drain regions. This implant is sometimes referred to as a lightly doped drain (LDD) implant and is self-aligned with polysilicon gate electrode
108
.
Next, as shown in
FIG. 1C
, a layer of dielectric
110
is deposited on the wafer surface, covering both the gate oxide
102
and the gate electrode
108
. The wafer is then subjected to an anisotropic etch which removes the dielectric
110
and gate oxide
102
on all exposed horizontal surfaces. The remaining dielectric
110
provides vertical spacers
112
. It should be noted that the terms “horizontal” and “vertical” are used herein relatively and with reference to a major surface of a semiconductor wafer, and may be interchanged. The spacers
112
act as an ion implantation mask for subsequent ion implant procedures which are used to dope portions of the substrate
101
adjacent to the gate electrode
108
in order to create or complete (depending on whether an LDD implant was performed) source
114
and drain
116
regions, as shown in FIG.
1
D. The spacers
112
, together with the remaining gate oxide
102
, separate the poly gate
108
from the source
114
and drain
116
regions.
As shown in
FIG. 1E
, after ion implantation, a silicide (e.g., WSi
2
) may be deposited on the gate electrode. Alternatively, a refractory metal, such as titanium (Ti) or cobalt (Co), may be deposited on the wafer surface, and silicide layers
120
,
122
and
124
are formed on the poly gate
108
, source
114
, and drain
116
regions, respectively, by reaction with the underlying poly/silicon by an alloy step well known in the art. Then, unreacted Ti is removed by a selective wet etch process, also well known in the art.
The conventional process of
FIGS. 1A-1E
results in the formation of silicide on the top surface of the gate providing a thin surface layer of improved conductivity. Both of these methods can lower the gate electrode resistance to about 1-10 &OHgr;/[ ], and are compatible with subsequent high temperature steps in semiconductor processing. Until now, most processes did not require additional reductions in resistance. However, deep sub-micron device sizes require more significant reductions in resistance.
In order to further reduce resistance in polysilicon gates, several additional approaches have been proposed. In one approach, the silicide in a conventional process, such as that described above, is replaced with selectively deposited metal, such as described in V. V. Lee et al., A selective CVD metal local interconnect technology. IEEE Proceedings of the Int'l. Electron Devices Mtg. 1988 (IEDM 88), pp. 450-53. Since metals have much lower resistivities than silicides, resistance in the polysilicon gate electrode is further reduced. Another approach involves forming a silicide layer on the sidewalls of the gate as well as the top surface, such as described in U.S. Pat. Nos. 5,227,320 and 5,306,951. By enlarging the surface area of the gate electrode covered by silicide relative to the conventional silicide process, signal propagation through the gate is improved.
Still another strategy for reducing resistance in MOS transistor gates involves replacing the polysilicon gate material with a material having a lower resistance, such as a metal, such as described by Chatterjee et al., Sub-100 nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process. IEEE Proceedings of the Int'l. Electron Devices Mtg. 1997 (IEDM 97), 821-24. This process is illustrated in
FIGS. 2A-C
. In
FIG. 2A
, a partially-formed semiconductor device is shown. The device
200
includes a silicon substrate
202
with implanted source
203
and drain
204
regions defining a channel region
206
in the substrate
202
. The substrate
202
is covered by a gate dielectric
208
, typically silicon dioxide. A polysilicon (“poly”) gate electrode
210
is positioned above the channel region
206
in the substrate
202
. The poly gate electrode is bounded by dielectric spacers
212
. This fabrication is achieved by conventional semiconductor processing techniques well known in the art. During its fabrication to this stage, the device
200
was covered with a layer of isolation oxide
214
and then planarized by CMP until the top surface
216
of the poly gate electrode is exposed.
As shown in
FIG. 2B
, the polysilicon gate electrode material is then removed by a wet etch process well known in the art, exposing the channel region
206
in the substrate
202
. Next, as shown in
FIG. 2C
, after a deglaze, an ultrathin gate oxide insulator
218
is grown by RTO, and possibly modified to form N-RTO by a remote plasma nitridization process following oxidation. Then, CVD titanium nitride (TiN)
220
is deposited on the gate dielectric followed by either aluminum (Al) or tungsten (W) deposition as the bulk of the replacement gate electrode material
222
. These metal materials have a resistivity about an order of magnitude lower than suicides and offer corresponding advantages for gate electrode conductivity. Further processing may be conducted to produce the T-shaped gate structure illustrated in FIG.
2
C.
While this structure provides a lower-resistance gate that conventional devices, it has a number of drawbacks. First, such a structure may have reliability issues since the TiN and metal/oxide interface is not well characterized in the art, in contrast to the well understood polysilicon/oxide interface.
Second, since the wet etch used to remove the poly gate electrode material
210
also removes the underlying gate oxide
208
, a new gate oxide
218
must b
Altera Corporation
Beyer Weaver & Thomas LLP
Williams Alexander O.
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