Low resistance contact between integrated circuit metal levels a

Details Low resistance contact between integrated circuit metal levels a Low resistance contact between integrated circuit metal levels a

1997-07-17

1999-05-18

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438637, 438638, 438666, 438672, H01L21/44

Patent

active

059045655

ABSTRACT:
A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.

REFERENCES:
patent: 5529953 (1996-06-01), Shoda
patent: 5686354 (1997-11-01), Avanizo et al.
patent: 5705849 (1998-01-01), Zheng et al.
Paper titled, "Ultra-Law, Resistance Direct Contact Cu Via Technology Using In-situ Chemical Vapor Cleaning", by Y. Tsuchiya, K. Ueno, V. M. Donnelly, T. Kikkawa, Y. Hayashi, A. Kobayashi and A. Sekiguchi published in the 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 59-60.

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