Low profile stacked multi-chip semiconductor package with...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S704000, C257S777000, C257S787000

Reexamination Certificate

active

06713857

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a stacked multi-chip semiconductor package in which at least two chips are stacked and mounted to a chip carrier formed with an opening, and a method for fabricating the semiconductor package.
BACKGROUND OF THE INVENTION
Multi-chip semiconductor packages employ advanced packaging technology to incorporate at least two chips in a single semiconductor package, so as to desirably provide a multiplied level of functionality and data storage capacity for the semiconductor package. Such a high-integration package assembly is suitably applied to high-level electronic devices sought for improved operational and electrical performances.
Image sensor chips are light-induced chips, and an active surface (where electronic elements and circuits are formed) of the image sensor chip is operationally driven by light. Therefore, for packaging the image sensor chip, a specially structured encapsulant is utilized to allow light to reach the chip. With the chip being mounted on a chip carrier such as substrate or lead frame, an encapsulant is formed on the chip carrier around the chip to encompass a cavity for receiving the chip therein; then, a transparent lid is attached to the encapsulant and covers the cavity, so as to allow light to penetrate through the lid to reach and drive the chip. Alternatively, an encapsulant made of a transparent material can be formed on the chip carrier to encapsulate the chip, and allows the chip to receive light through the transparent encapsulant.
A multi-chip semiconductor package with an image sensor chip can be fabricated by the following processes. First, a first chip is mounted on a substrate, and a second chip or image sensor chip is stacked on the first chip. An encapsulant is formed on the substrate around the first and second chips, and encompasses a cavity for receiving the first and second chips therein. Then, a transparent lid is provided to cover the cavity, such that light can penetrate through the lid to reach and induce operation of the second chip (image sensor chip). However, this stacked multi-hip package may have relatively large structural size in consideration of combined thickness of the first and second chips, thereby making the package not effectively compact in profile.
Therefore, it would be greatly desired to provide multi-chip package structure incorporated with at least an image sensor chip with reduced package size.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a stacked multi-chip semiconductor package and a fabrication method thereof, which can incorporate an image sensor chip in multi-chip structure, so as to improve operational performances of the image sensor chip, and help reduce overall size of the semiconductor package.
In accordance with the above and other objectives, the present invention proposes a stacked multi-chip semiconductor package and a fabrication method thereof The semiconductor package comprises: a chip carrier having a first surface and a second surface opposed to the first surface, and formed with at least an opening penetrating through the chip carrier; at least a first chip received within the opening of the chip carrier; at least a second chip mounted on the second surface of the chip carrier and over the opening, and stacked on the first chip via an adhesive, a first encapsulant formed on the first surface of the chip carrier, and filling into the opening of the chip carrier for encapsulating the first chip; a second encapsulant formed on the second surface of the chip carrier around the second chip, wherein the second encapsulant encompasses a cavity for receiving the second chip within the cavity; and a lid attached to the second encapsulant for covering the cavity.
A fabrication method of the above semiconductor package comprises the steps of: preparing a chip carrier having a first surface and a second surface opposed to the first surface, wherein at least an opening is formed through the chip carrier; applying an adhesive tape on the second surface of the chip carrier and over the opening, allowing the adhesive tape to be partly exposed to the opening; mounting at least a first chip within the opening of the chip carrier, and attaching the first chip to the adhesive tape; forming a first encapsulant on the first surface of the chip carrier, the first encapsulant filling into the opening of the chip carrier for encapsulating the first chip; removing the adhesive tape from the second surface of the chip carrier; forming a second encapsulant on the second surface of the chip carrier at area outside the opening to encompass a cavity, mounting at least a second chip within the cavity on the second surface of the chip carrier and over the opening, and stacking the second chip on the first chip via an adhesive; and attaching a lid to the second encapsulant for covering the cavity.
The first chip may be a driver chip, and the second chip may be an image sensor chip. The above semiconductor package provides multi-chip package structure to stack the image sensor chip (second chip) on the driver chip (first chip) that helps drive operation of the image sensor chip, so as to improve functionality and operational performances for the package structure with the image sensor chip. Moreover, the driver chip is received within an opening formed through a chip carrier where the image sensor chip is mounted, such that overall package thickness or size would not be increased but package integration is effectively enhanced by virtue of stacked multi-chip structure, which is a significant benefit in packaging technology. Furthermore, an elastomer adhesive is used for stacking the image sensor chip on the driver chip, and thus reduces stress and delamination in the package structure during fabrication processes.


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patent: 6057597 (2000-05-01), Farnworth et al.
patent: 6353257 (2002-03-01), Huang
patent: 2002/0113304 (2002-08-01), Doh et al.
patent: 2002/0130398 (2002-09-01), Huang
patent: 2002/0135080 (2002-09-01), Bai
patent: 2003/0025199 (2003-02-01), Wu et al.

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