Low profile stacked multi-chip package and method of forming...

Details Low profile stacked multi-chip package and method of forming... Low profile stacked multi-chip package and method of forming...

2001-09-30

2004-02-24

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257S777000, C361S736000

Reexamination Certificate

active

06696320

ABSTRACT:

TECHNICAL FIELD
This disclosure relates generally to integrated circuits, and in particular but not exclusively, relates to integrated circuit packaging.
BACKGROUND
Many integrated circuits (i.e., chips) have a need for a large number of input and/or output (I/O) connections off the chip. However, typical chips use the periphery of the chip to provide I/O connections, which works well with conventional wire bonding technology to implement the off-chip connections. Relatively new flip chip technology can be used to provide an increased number of I/O connections on the circuit side of the chip. Flip chips typically use conductive “bumps” formed on the surface of the circuit side of the flip chip, which are used to make off-chip connections to corresponding conductive regions on an interconnect substrate (e.g., ceramic, flexible tape), or printed wiring board or other interconnect structure.
However, the demand continues for even more I/O connections. At the same time, users typically desire a thin profile or pitch when the chips are packaged, along with short interconnections to facilitate high-speed signal transmission. Current solutions have problems addressing these sometimes conflicting needs.


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