Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-04-23
2003-04-29
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000, C257S723000, C257S784000, C257S780000, C257S787000, C257S738000
Reexamination Certificate
active
06555919
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a multi-chip semiconductor package mounted with stacked chips therein.
BACKGROUND OF THE INVENTION
Stack semiconductor packages are advanced packaging technology, which is characterized by stacking a plurality of chips in a single package structure, so as to desirably multiply operational performances and memory capacity for semiconductor packages.
Conventional chip-stack structures are exemplified with reference to
FIGS. 5A and 5B
. As shown in
FIG. 5A
, two chips
10
,
11
are stacked on a substrate
12
, and electrically connected to the substrate
12
by means of bonding wires
13
,
14
respectively. Such a structure is limited to a relatively smaller size of the overlying chip
11
with respect to the underlying chip
10
, whereby forming of the bonding wires
13
would not be interfered by stacked arrangement of the chips
10
,
11
. A solution to chip-size limitation, as shown in
FIG. 5B
, is to apply an adhesive
15
between the two chips
10
,
11
in a manner that, the adhesive
15
is sufficiently dimensioned in thickness for allowing the overlying chip
11
to be mounted on the underlying chip
10
without coming into contact with the bonding wires
13
, such that the overlying chip
11
can be sized equally or even larger in surface area than the underlying chip
10
.
However, in the above chip-stack structures, the bonding wires
13
,
14
may be easily subject to wire sagging or sweep due to strong mold-flow impact of a molding compound or resin for forming a chip-enclosed encapsulant (not shown) during a molding process. Wire sagging or sweep would cause electrical contact or short circuit between adjacent bonding wires or between bonding wires and chips, thereby undesirably damaging electrical quality and yield for fabricated products.
Moreover, as the different sets of bonding wires
13
,
14
laterally extend to reach different area on the substrate
12
outside the underlying chip
10
, occupied area on the substrate
12
is therefore hardly reduced. Further, wire loops of the bonding wires
14
bonded to the overlying chip
11
are essentially adapted in elevation to allow the wire lateral extension to reach farther than the bonding wires
13
bonded to the underlying chip
10
; this makes overall structural thickness or height hardly reduced in consideration of loop height of the bonding wires
14
.
In order to solve the wire sweep or short circuit problems, a plurality of sweep-prevention mechanisms have been disclosed in the art, to name a few herein as follows with reference to
FIGS. 6 and 7
.
FIGS. 6A and 6B
illustrate pre-encapsulation of bonding wires in a conventional chip assembly structure. As shown in
FIG. 6A
, bonding wires
20
for electrically connecting a chip
21
to a substrate
22
are strictly attached at original bonding positions by a resin compound
23
prior to forming of an encapsulant
24
. Therefore, during a molding process for fabricating the encapsulant
24
, the bonding wires
20
held in position within the resin compound
23
would not be subjected to wire sagging or sweep by mold-flow impact. Alternatively, as shown in
FIG. 6B
, a resin compound
23
is used to partly encapsulate the bonding wires
20
, and to hold the bonding wires
20
in position without being sagged or swept during molding and without coming into contact with adjacent wires (not shown) or edge of a chip
21
, thereby preventing short circuit from occurrence in a perfect manner.
FIGS. 7A and 7B
illustrate forming of a dam structure in a conventional chip assembly structure. As shown in
FIG. 7A
, a dam structure
30
is formed on a substrate
31
, whereby bonding wires
32
for electrically connecting the chip
33
to the substrate
31
, are supported by the dam structure
30
in a manner as not to come into contact with the chip
33
, so that wire-to-chip short circuit can be effectively prevented. Alternatively, as shown in
FIG. 7B
, the dam structure
30
can be formed on the chip
33
, and provides the same improvement as to space the bonding wires
32
apart from the chip
33
, without causing short circuit between the bonding wires
32
and the chip
33
.
However, the above sweep-prevention mechanisms can only solve the wire sweep or shirt circuit problems for the conventional chip-stack structures, without achieving any improvement in profile reduction for the chip-stack structures. And, the above conventional chip-stack structures are primarily used to accommodate chips with peripherally-situated bond pads where bonding wires are bonded, but not suitably applied for stacking chips with centrally-situated bond pads such as DRAM (dynamic random access memory) chips.
Therefore, it is highly desired to develop a semiconductor package for stacking chips with centrally-situated bond pads, by which package profile can be desirably miniaturized as well as electrical quality can be firmly assured.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a low profile stack semiconductor package for use to stack chips having centrally-situated bond pads, such as DRAM (dynamic random access memory) chips.
Another objective of the invention is to provide a low profile stack semiconductor package, which effectively reduces occupied area on a substrate and overall thickness of the package structure, in favor of profile miniaturization for the semiconductor package.
A further objective of the invention is to provide a low profile stack semiconductor package, which significantly prevents undesirable contact or short circuit between bonding wires and a chip.
A further objective of the invention is to provide a low profile stack semiconductor package, which allows bonding wires to be firmly held in position, without causing wire sagging or sweep.
A further objective of the invention is to provide a low profile stack semiconductor package, which can desirably reduce pitch spacing between adjacent bonding wires, allowing the semiconductor package to be suitably applied to high-level products with fine-pitch structural arrangement.
In accordance with the above and other objectives, the present invention proposes a low profile stack semiconductor package, comprising: a substrate having an opening penetrating therethrough; a first chip formed with a plurality of centrally-situated bond pads on an active surface thereof, and mounted on the substrate in a manner as to expose the bond pads to the opening of the substrate; a second chip formed with a plurality of centrally-situated bond pads on an active surface thereof, and mounted on the first chip in a manner that, the active surface of the second chip is opposed to the active surface of the first chip, wherein a cushion member is formed at peripheral area on the active surface of the second chip, and extends outwardly to at least reach a peripheral edge of the active surface; a plurality of first bonding wires for electrically connecting the bond pads of the first chip through the opening to the substrate; a plurality of second bonding wires for electrically connecting the bond pads of the second chip to the substrate in a manner that, the second bonding wires extend from the bond pads in a direction substantially parallel to the active surface of the second chip, and are adapted to be in contact with the cushion member, beyond which the second bonding wires turn to be directed toward the substrate; an encapsulant for encapsulating the first and second chips, and the first and second bonding wires; and a plurality of solder balls implanted on the substrate and exposed to outside of the encapsulant, for electrically connecting the first and second chips to an external device.
The above semiconductor package characterized by forming a cushion member and parallel extension of second bonding wires, would provide significant benefits. First, the second bonding wires extending in parallel to the second chip and free of forming wire loops, help reduce overall thickness of the semiconductor
Shan Wei-Heng
Tsai Chung-Che
Talbott David L.
Thai Luan
Ultratera Corporation
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