Low profile, chip-scale package and method of fabrication

Details Low profile, chip-scale package and method of fabrication Low profile, chip-scale package and method of fabrication

2007-12-18

2007-12-18

Parekh, Nitin (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S109000, C438S110000, C438S127000, C257SE23024, C257S686000

Reexamination Certificate

active

11470306

ABSTRACT:
Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body attached. A semiconductor chip is positioned in the opening while leaving a gap to the substrate; the chip has an active surface including at least one bond pad, and a passive surface substantially coplanar with the second substrate surface. Substrate thickness and chip thickness may be substantially equal. Bonding elements bridge the gap to connect electrically bond pad and routing strip. Encapsulation material protects the active chip surface and the bonding elements, and fills the gap so that the filler surface is substantially coplanar with the passive chip surface and the second substrate surface. The support tape used in assembly is discarded.

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