Low pressure baked HSQ gap fill layer following barrier layer de

Details Low pressure baked HSQ gap fill layer following barrier layer de Low pressure baked HSQ gap fill layer following barrier layer de

1998-05-15

2000-04-04

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438627, 438624, 438631, 438645, 438648, 438653, 438658, 438660, 438666, 438672, H01L 214763

Patent

active

060461047

ABSTRACT:
Via void formation is substantially reduced or eliminated between the steps of depositing a barrier layer on a HSQ gap fill layer, and filling a through-hole with a conductive material deposited on the barrier layer, by performing a low-temperature baking following the deposition of the barrier layer. In particular, a high-temperature, low-pressure degas operation is performed immediately preceding, and in-situ with, the tungsten plug deposition that fills the through-hole to form a via. The low-pressure baking is performed at a high temperature and sufficiently low pressure that is less than the vapor pressure of imparities contained in the HSQ. Hence, any exposed portions of the HSQ gap fill layer that are not covered by the barrier layer (e.g., the titanium nitride (TiN) liner) will be outgassed during the low-pressure baking to minimize the possibility of HSQ outgas during tungsten deposition.

REFERENCES:
patent: 5866945 (1999-02-01), Chen et al.
patent: 5888898 (1999-03-01), Ngo et al.
patent: 5888911 (1999-03-01), Ngo et al.
patent: 5925932 (1999-07-01), Tran et al.
patent: 5942801 (1999-08-01), Tran

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