Low pre-heat pressure CVD TiN process

Details Low pre-heat pressure CVD TiN process Low pre-heat pressure CVD TiN process

2000-08-31

2002-06-11

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S675000, C438S685000, C438S627000, C438S629000, C438S637000, C438S643000, C438S648000

Reexamination Certificate

active

06403478

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention generally relates to the manufacturing of integrated circuits, and more particularly to a method of improving the reliability of titanium nitride (TiN) vias using chemical vapor deposition (CVD) in the integrated circuit manufacturing process.
(2) Description of Prior Art
The term via is used to describe interconnection between two metal interconnection layers in a semiconductor. In a typical application for an integrated circuit manufacturing process, a via opening is etched through a dielectric layer to an underlying conductor or conductive area to which an electrical contact is to be made. Titanium nitride (TiN) is typically used in CVD to line the walls of the via opening since it will not react with underlying doped silicon structures during subsequent high temperature processing. The via opening is subsequently filled with a metal such as Tungsten (W). A “Kelvin” via is a single, isolated via positioned over a large metal pad.
Refer now to
FIG. 1
showing a typical mechanism for performing chemical vapor deposition (CVD). For the CVD TiN process, the wafer
100
is moved into the deposition chamber
102
and preheated to remove any thermal history. The wafer heater
104
is set to approximately 450° C., but the actual wafer
100
temperature only reaches about 380° C. To prevent any heat loss to the showerhead
106
during the heating stage, the wafer
100
and heater
104
are lowered away from the showerhead
106
using the positioning mechanism
114
. Meanwhile, the chamber
102
is depressurized to 5 Torr using the pump
108
and pressure control valve
112
while the chamber
102
is purged with argon and nitrogen through the gas inlet
110
. Gas flows are adjusted to optimize heat transfer and temperature uniformity of the wafer
100
. Since the wafer
100
is only resting on the heater
104
, the gas cushion between them is the mechanism for most of the thermal conduction. However, with the pressure set to 5 Torr, the wafer
100
temperature overshoots to a peak of 395° C. during this preheating step before settling at approximately 380° C. The deposition process is then completed as is typical in the art where the showerhead
106
is positioned, the gas flow and pressure are set, and the deposition is performed.
Referring now to
FIG. 2
showing a via contact
214
and a completed Kelvin via
216
. A substrate
200
is provided which may contain active semiconductor devices (not shown) such as transistors. Conducting metal lines
202
may be patterned on the substrate
200
. A dielectric layer
204
such as SiO
2
is patterned over the metal lines
202
and substrate
200
. Via openings
210
are the etched into the dielectric layer
204
exposing the semiconductor devices (not shown) and metal lines
202
. Typically a glue layer of titanium (not shown) is patterned to line the via opening
210
, followed by a barrier metal
206
, typically titanium nitride (TiN). The via opening
210
is then filled with a conducting material
208
such as Tungsten (W).
Using this prior art recipe, Kelvin via resistances above 100 &OHgr;/via are observed. Acceptable Kelvin vias have a resistance of typically less than 20 &OHgr;/via. Using a scanning electron microscope (SEM), a cross section of the via shows that the underlying metal protrudes into the via opening on Kelvin vias with high resistance. This problem is illustrated in
FIG. 3. A
stress void
212
forms in the conducting metal line
202
and significantly reduces the via contact area. This results in higher resistance in the Kelvin via
216
and often intermittent circuit operation. It is believed that the overshoot in wafer temperature during the preheating process during TiN CVD is the cause of the stress voids
212
, forcing the conducting metal line
202
to protrude into the via opening
210
.
Other approaches attempt to address problems associated with forming contacts and vias. U.S. Pat. No. 5,789,321 to Ohshita teaches a method of CVD TiN using TiCl
4
and a nitrogen source where the silicon is heated to 500° C. and the chamber pressure is 0.15 Torr. U.S. Pat. No. 5,840,628 to Miyamoto teaches a method using a plasma enhanced CVD (PECVD) TiN two-step deposition. U.S. Pat. No. 5,246,881 to Sandhu et al teaches a via process where the substrate is heated to 200-600° C. (400° C. optimum) and the chamber pressure is reduced to 0.1 to 100 Torr (preferably 0.5 Torr). U.S. Pat. No. 5,561,106 to Foster et al teaches a method using ammonia in the TiN CVD process. Here, the substrate is heated to between about 400° C. to 500° C. and the chamber pressure is between 0.5 and 20 Torr.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method of fabricating a reliable contact in the manufacture of an integrated circuit device.
Another object of the present invention is to prevent the intermittent high Kelvin via resistance in a contact.
Another object of the present invention is the prevention of the wafer temperature overshoot during the CVD warm-up step.
Another object of the present invention is the prevention of intermittent high Kelvin vias by preventing the wafer temperature overshoot prior to barrier metal deposition.
Yet another object of the present invention is the prevention of intermittent high Kelvin vias by preventing the wafer temperature overshoot by lowering the chamber pressure during warm-up prior to barrier metal deposition.
Yet another object of the present invention is the prevention of intermittent high Kelvin vias by performing a plasma annealing step after deposition of the metal filling the via.
Accordingly, a new method for preventing intermittent high Kelvin vias by preventing the wafer temperature overshoot by lowering the chamber pressure during warm-up prior to barrier metal deposition is achieved. The present invention uses a chamber pressure of between 2 and 3 Torr during warm-up of the wafer prior to barrier metal deposition rather than 5 Torr, which is conventionally used. By reducing the pressure, the thermal conductivity between the wafer heater and the wafer is reduced, and the overshoot in the wafer temperature is minimized. This reduces the deposition rate by approximately 10 angstroms over a 15 second deposition. This is compensated for by an increase in deposition time. However, because the reaction is carried out in the reaction-limited regime, the step coverage will increase as the wafer temperature is reduced. This is followed by an N
2
/H
2
plasma annealing performed with a wafer temperature between about 350° C. and 420° C. The process is then completed by depositing and patterning the second metal layer.


REFERENCES:
patent: 5246881 (1993-09-01), Sandhu et al.
patent: 5610106 (1997-03-01), Foster et al.
patent: 5679981 (1997-10-01), Kuwajima
patent: 5789321 (1998-08-01), Ohshita
patent: 5840628 (1998-11-01), Miyamoto
patent: 5861675 (1999-01-01), Sasaki et al.
patent: 6136691 (2000-10-01), Chen
patent: 6159853 (2000-12-01), Iai
patent: 6215186 (2001-04-01), Konecni et al.

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