Low power type Rambus DRAM

Details Low power type Rambus DRAM Low power type Rambus DRAM

2002-07-26

2003-11-11

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S227000, C365S233100

Reexamination Certificate

active

06646939

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to Rambus DRAM, and more particularly, to Rambus DRAM capable of reducing power consumption by controlling top and bottom serial/parallel shifter blocks to independently operate according to received bank address.
2. Description of the Related Art
Generally, Rambus DRAM has two data storage areas and one I/O block for input/output, wherein data shifter blocks are connected to the data storage areas in one to one correspondence to interface therebetween.
FIG. 1
is a block diagram of Rambus DRAM according to conventional method, comprising an interface logic circuit unit
1
, a DLL unit
2
, an I/O unit
3
, top serial/parallel shifter unit
4
, bottom serial/parallel shifter unit
5
, a top memory bank unit
6
and lower memory bank unit
7
.
When Read command or Write command is applied from the external, the interface logic circuit unit
1
generates W
1
signal in case of Write command and generates R
1
signal in case of Read signal.
The DLL unit
2
generates W
2
clock signals responding to the W
1
signal received from the interface logic circuit unit
1
and generates R
2
clock signal responding to the R
1
signal received from the interface logic circuit unit
1
.
The W
2
signal and the R
2
signal generated in the DLL unit
2
are applied to the I/O unit
3
and then, buffered into W
3
and R
3
signals The buffered W
3
and R
3
signals are applied to top and bottom serial/parallel shifter units
4
and
5
, simultaneously.
The top and bottom serial/parallel shifter units
4
and
5
convert data received from the external into parallel data according to the W
3
signal received from the I/O unit
3
in write operation, and convert parallel data received from the top and bottom memory bank units
6
and
7
into serial data according to the R
3
signal received from the I/O unit
3
in read operation and output the result.
The conventional Rambus DRAM has top and bottom memory bank units
6
and
7
comprising
16
memory banks, wherein one of top and bottom memory bank units
6
,
7
is operated in one read or write operation.
However, according to the conventional Rambus DRAM, R
3
and W
3
signals, which are generated from the I/O unit
3
, are simultaneously inputted to top and bottom serial/parallel shifter units
4
and
5
and thereby, both of them unnecessarily operate in read or write operation. Therefore, clock toggling is generated in one shifter block unnecessarily operating in read or write operation and power consumption is increased.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above problems and the object of the present invention is to provide Rambus DRAM reducing power consumption by controlling top and bottom serial/parallel shifter blocks to independently operate according to received bank address.
In order to accomplish the above object, the present invention comprises: a top memory bank unit comprising a plurality of banks for storing data; a bottom memory bank unit comprising a plurality of banks for storing data; a top serial/parallel shifter unit connected between the top memory bank unit and input/output block unit for converting data received by read or write command into serial or parallel data and outputting the result; and a bottom serial/parallel shifter unit connected between the bottom memory bank unit and input/output block unit for converting data received by read or write command into serial or parallel data and outputting the result, the Rambus DRAM including an interface logic circuit unit for generating first read clock signal R
1
and top read selection signal R_top or bottom read selection signal R_bot for selecting the top or the bottom memory bank unit according to read command received from the external and generating first write clock signal W
1
and top write selection signal W_top or bottom write selection signal W_bot for selecting the top or the bottom memory bank unit according to write command received from the external; a delay lock loop (DLL) unit for receiving the first write clock signal W
1
to generate first write clock signal W
2
and receiving the first read clock signal R
1
to generate synchronized second read clock signal R
2
; and an input/output block unit for generating signals for selectively controlling the operation of top serial/parallel shifter unit or bottom serial/parallel shifter unit by buffering the first write clock signal W
2
or the first read clock signal R
2
received from the DLL according to the top read selection signal R_top, the bottom read selection signal R_bot, the top write selection signal W_top and the bottom write selection signal W_bot received from the interface logic circuit unit.


REFERENCES:
patent: 6310814 (2001-10-01), Hampel et al.
patent: 6362995 (2002-03-01), Moon et al.
patent: 6552955 (2003-04-01), Miki
patent: 2001/0015934 (2001-08-01), Kwak

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