Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-28
2003-09-09
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000
Reexamination Certificate
active
06617643
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to Metal-Oxide Semiconductor (MOS) devices, and more particularly to a low power, three-terminal tunneling MOS device having operational characteristics that are a hybrid between a MOS transistor, a gated diode and a tunneling diode.
BACKGROUND OF THE INVENTION
A conventional n-type Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) is shown in the cross-sectional diagram of FIG.
1
. The MOSFET
10
consists of a source
12
and a drain
14
, two highly conducting n-type semiconductor regions that are isolated from the p-type semiconductor substrate
16
by reversed-biased p-n diodes. A gate electrode
18
generally covers the region between source and drain and is separated from the semiconductor by the gate oxide
20
.
The applied voltage will determine which n-type region provides the electrons and becomes the source
12
, while the other n-type region collects the electrons and becomes the drain
14
. The voltages applied to the drain and gate, as well as, to the substrate
16
by way of the back contact
22
are referred to as the source potential.
The voltage applied to the gate electrode
18
controls the flow of electrons from the source
12
to the drain
14
. A positive voltage applied to the gate electrode attracts electrons to the interface between the gate oxide
20
and the semiconductor substrate
16
. These electrons form a conducting channel between the source and the drain, referred to as the inversion layer
24
. As shown the inversion layer
24
is formed adjacent to the gate oxide
20
above the depletion layer
26
. Gate current is not required to maintain the inversion layer at the interface since the gate oxide blocks any carrier flow. The net result is that the voltage that is applied to the gate controls the current between drain and source.
FIG. 2
is a plan view diagram of the MOSFET of FIG.
1
. The plan view diagram illustrates the gate electrode length L, and the gate electrode width W. Note that the gate electrode length is not defined as the actual physical length of the gate electrode
18
, but rather the gate length is defined as the distance between the source region
12
and the drain region
14
. The overlap between the gate electrode and the source and drain region is required to ensure that the inversion layer
24
forms a continuous conducting path between the source and drain regions. Typically, this overlap is kept to a minimum in order to minimize parasitic capacitance in the device. In conventional MOSFET devices variances in the length of the gate electrode will affect the turn-on voltage of the device. In this regard, larger gate length devices will require more turn-on voltage and smaller gate length devices will require less turn-on voltage.
Low power electronics based on the style of Complementary Metal Oxide Semiconductors (CMOS) is principally driven by a reduction in the power supply voltage. This is due to the power consumed by a CMOS circuit being primarily due to the charging/discharging of capacitances in the circuit. This power can be defined as P=½CV
2
f, where C is the capacitance of the circuit, V is the power supply voltage, and f is the frequency of the circuit. This relationship makes it apparent that the power is dependent on the square of the voltage.
The second factor that is driving down the CMOS power supply is the scaling of the individual transistors, and the resulting reliability and performance constraints on the power supply voltage. The drive current that can be conducted by a MOS transistor is directly related to the power supply voltage, thus simply reducing the voltage, reduces the drive current, which results in a decrease in the speed and hence the performance of the circuit. Scaled devices are designed to maintain the current drive as much as possible.
One of the variables available to the device designer is the threshold voltage (the transition voltage required to turn the device from an off state to an on state) which determines the drive current. Reducing the threshold voltage increases the drive current of the transistor, however, if the threshold voltage is reduced too far, the off-current of the transistor increases. The off-current needs to remain low to minimize the power consumed due to leakage currents and also to enable the circuit to utilize dynamic logic. The off-current will increase for two principle reasons: the sub-threshold slope and the short channel effect. There is a maximum theoretical rate at which a transistor current will decrease as the gate voltage is decreased. This rate is referred to as the sub-threshold slope and it sets a minimum value for the threshold voltage. In addition, as the transistor is scaled down in size, the threshold voltage tends to decrease and the sub-threshold slope worsens. This further increases the minimum value of the designed threshold voltage. Additionally, variations in the processing leads to variations in the gate length of the transistor and hence variations in the threshold voltage. Thus, the transistor must be designed to have a high enough threshold voltage to maintain a minimum off-current for the shortest transistor.
Much of the effort to date in low power electronics has been focused on silicon-on-insulator (SOI) MOS transistors. These devices have steeper sub-threshold slopes due to the thin silicon channels and reduced parasitic capacitances due to the buried insulator film.
In electrical devices fabricated with semiconductor materials an electron tunneling effect can be realized by forming a junction between a highly doped P-type semiconductor material and a highly doped N-type semiconductor material. The junction provides for a negative resistance characteristic, whereby, as the forward voltage across the junction is increased the current through the junction decreases. The negative resistance characteristic has been beneficially implemented in amplifiers, mixers, oscillators, detectors and the like.
The tunneling of electrons at the PN junction occurs most effectively when a high electric field exists in the semiconductor. For example, tunneling can most readily occur within a reverse-biased depletion region of a silicon PN junction. A narrow depletion region can be achieved when the doping level of the P-type and N-type materials is high, typically on the order of about 1E18 atoms per cubic centimeter (cm
3
) or higher. The narrow depletion region allows for electrons to tunnel from the P side to the N side where otherwise they would not be prone. The phenomenon in which the valence band electrons penetrate through the energy gap into empty conduction band states is termed “tunneling”.
Most tunneling devices, to date, have been two-terminal diode type devices. While the two-terminal devices are advantageous in many applications, such devices are typically required to be integrated with other devices to achieve an overall circuit function. In addition, the two-terminal device does not typically lend itself to controlling the tunneling effect without implementation of external circuits. Thus, a need exists to develop a semiconductor device having tunneling capabilities and more than two terminals to allow for control of the device characteristics. In addition, such a device will benefit from having a smaller gate voltage transition between the off-current and on-current states and which also has less dependence on the lateral dimensions of the device. Additionally, a need exists to develop a semiconductor device that exhibits other beneficial electrical characteristics beyond negative resistance characteristics to thereby enhance the applicability of such devices.
SUMMARY OF THE INVENTION
The present invention provides for a three terminal tunneling device that has a smaller voltage transition between off-current and on-current states and which also has less dependence on the lateral dimensions of the device. The device is a hybrid between a MOS transistor, a gated diode and a tunneling diode.
The semiconductor device of the present invention will includ
Alston & Bird LLP
Fahmy Wael
MCNC
Pham Hoai
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