Low power set associative cache memory

Details Low power set associative cache memory Low power set associative cache memory

1993-01-25

1999-06-15

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711128, 39575005, 39575006, G06F 1208

Patent

active

059132230

ABSTRACT:
A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus.

REFERENCES:
patent: 4933835 (1990-06-01), Sachs
patent: 5018061 (1991-05-01), Kishigami et al.
patent: 5019971 (1991-05-01), Lefsky et al.
patent: 5185878 (1993-02-01), Baror et al.
patent: 5210845 (1993-05-01), Crawford et al.

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