Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-09-13
2005-09-13
Nguyen, T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S113000, C711S118000, C711S136000
Reexamination Certificate
active
06944713
ABSTRACT:
A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.
REFERENCES:
patent: 5559986 (1996-09-01), Alpert et al.
patent: 5715426 (1998-02-01), Takahashi et al.
patent: 6389523 (2002-05-01), Shimazaki et al.
patent: 6594728 (2003-07-01), Yeager
patent: 6601154 (2003-07-01), Shimazaki et al.
patent: 6687789 (2004-02-01), Keller et al.
patent: 6718439 (2004-04-01), Jayavant
patent: 0 330 007 (1989-08-01), None
Hollenbeck et al: “PA700LC integrates cache for cost/performance” Digest of papers of Compcon. , Los Alamitos, IEEE Comp. Soc. Press. 1996. pp. 170.
Dave Hollenbeck et al, PA7300LC Intergrates Cache for Cost/Performance, Feb. 25, 1996 IEEE, pp. 167-174, XP010160890.
Richard E. Matick , Functional cache chip for improved system parformance , Jan. 1989 , pp. 15-31 , XP000050855.
Clark Lawrence T.
Miller Jay B.
Intel Corporation
Nguyen T.
Parker Lanny L.
LandOfFree
Low power set associative cache does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low power set associative cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power set associative cache will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3375666