Low power semi-trace instruction/trace hybrid cache with...

Details Low power semi-trace instruction/trace hybrid cache with... Low power semi-trace instruction/trace hybrid cache with...

2004-02-26

2008-10-14

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S129000, C711S137000

Reexamination Certificate

active

07437512

ABSTRACT:
A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution.

REFERENCES:
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patent: 6473331 (2002-10-01), Takashima
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patent: 2004/0015675 (2004-01-01), Kyker et al.
patent: 2004/0088489 (2004-05-01), Hironaka et al.
patent: 2005/0125613 (2005-06-01), Kim et al.
patent: 2005/0132169 (2005-06-01), Mates
Rotenberg, E.; Bennett, S.; Smith, J.E., Trach cache: a low latency approach to high bandwidth instruction fetching, Microarchitecture, 1996. MICRO-29. Proceedings of the 29th Annual IEEE/ACM International Symposium on , 1996, pp. 24-34.
Pending U.S. Appl. No. 10/750,256, filed Dec. 29, 2003 to Dennis M. O'Connor, et al.

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