Low power, self-gated, pulse triggered clock gating cell

Details Low power, self-gated, pulse triggered clock gating cell Low power, self-gated, pulse triggered clock gating cell

2009-07-14

2010-10-05

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S037000

Reexamination Certificate

active

07808279

ABSTRACT:
A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.

REFERENCES:
patent: 5498988 (1996-03-01), Reyes et al.
patent: 6552572 (2003-04-01), Cheung et al.
patent: 6822478 (2004-11-01), Elappuparackal
patent: 7023240 (2006-04-01), Elappuparackal
patent: 2003/0006806 (2003-01-01), Elappuparackal

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