Low power scan design and delay fault testing technique...

Details Low power scan design and delay fault testing technique... Low power scan design and delay fault testing technique...

2008-01-15

2008-01-15

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S016000, C714S727000

Reexamination Certificate

active

07319343

ABSTRACT:
A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

REFERENCES:
patent: 6577157 (2003-06-01), Cheung et al.
patent: 2003/0218478 (2003-11-01), Sani et al.
Xiaodong Zhang and Kaushik Roy,Power Reduction in Test-Per-Scan BIST, IEEE, 2000, no month.
Stefan Gerstendö{umlaut over ( )}rfer and Hans-Joachim Wunderlich,Minimized Power Consumption for Scan-Based Bist, pp. 77-84, ITC International Test Conference, IEEE, 1999, no month.
Kwang-Ting Cheng, Srinivas Devadas and Kurt Keutzer,A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits, pp. 403-410, International Test Conference 1991, IEEE 1991, no month.
Sumit DasGupta, Ronald G. Walther, Thomas W. Williams and Edward B. Eichelberger,An Enhanced to LSSD and Some Applications of LSSD in Reliability, Availability and Serviceability, pp. 289-291, Proceedings of FTCS-25, vol. III, IEEE, 1996, no month.

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