Low power RAM memory cell using a precharge line pulse...

Details Low power RAM memory cell using a precharge line pulse... Low power RAM memory cell using a precharge line pulse...

1998-11-25

2002-04-30

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000, C365S203000

Reexamination Certificate

active

06380592

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior European Patent Application No. 97-120943.2, filed Nov. 28, 1997, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically to a low power RAM memory cell having cross-coupled CMOS inverters.
2. Description of the Related Art
A conventional semiconductor static random access memory (SRAM) device is formed with static memory cells that each have six transistors.
FIG. 1
shows a conventional CMOS six transistor SRAM memory cell. The memory cell
1
includes a pair of cross-coupled CMOS inverters
2
and
3
, each of which is coupled to a bit line
4
and
5
. In particular, the first inverter
2
is coupled to a first bit line
4
through a bi-directional access device
6
, and the second inverter
3
is coupled to an adjacent second bit line
5
through a second access device
7
. During reading and writing operations, different voltages must be applied to the two bit lines
4
and
5
. Thus, this type of access to the storage node of the memory cell can be termed “differential.”
More specifically, during reading from the memory cell of
FIG. 1
, the bit line voltage swing amplitude is dependent upon the length of time the memory cell has been activated. The voltage difference caused by the swing can be kept quite small and sensed by the sense amplifier of the memory device in order to reduce power consumption. Further, during writing to the memory cell, the bit line voltage swing is made as large as possible (e.g., the full CMOS logic voltage level) in order to toggle (i.e., write to) the memory cell. Thus, in an SRAM six transistor memory cell array with m rows and n columns, the current consumption during reading and writing can be estimated using the following formulas:
Idd
r
=n*m*Cb*&Dgr;V/dt  (1)
Idd
w
=n*m*Cb*&Dgr;V
w
/dt  (2)
where n is the number of bits in the word being read or written, Cb is the bit line capacitance associated with a given cell, &Dgr;V
r
is the bit line voltage swing during a read operation, and &Dgr;V
w
is the bit line voltage swing during a write operation. Typically, &Dgr;V
w
corresponds to the supply voltage level Vdd.
Previous efforts to reduce the power consumed by such a memory matrix focus on changing one or more of the parameters in the above formulas. One such technique is disclosed by N. Kushiyama et al. in “A 295 MHz CMOS 1M (×256) embedded SRAM using I-directional read/write shared sense amplifiers and self-timed pulsed word-line drivers” (ISSCC Dig. Tech. Papers, February 1995, pages 182-183). According to this technique, power consumption is reduced by reducing the number of cells on the bit line through a hierarchical bit line scheme.
Another power reduction technique is disclosed by B. Amrutur and H. Horowitz in “Technique to reduce power in fast wide memories” (Dig. Tech. Papers, October 1994, Symp. on Low Power Electronics, pages 92-93). This technique reduces power consumption by limiting the bit line voltage swing during a read by controlling the word line pulse length. Yet another power reduction technique is disclosed by T. Blalock and R. Jager in “A high-speed clamped bit line current-mode sense amplifier” (IEEE J. Solid State Circuits, Vol. 26, No. 4, April 1991, pages 542-548). This solution also reduces power consumption by limiting the bit line voltage swing during a read, but does so using current-mode sense amplifiers so as to reduce &Dgr;V
r
. Still another power reduction technique limits the bit line voltage swing during a write to a predetermined value (i.e., Vdd−Vt) using NMOS transistors during precharging.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a RAM memory device with reduced power consumption. A RAM memory device is formed with memory cells that each have cross-coupled inverters, and the pull-down transistors of the inverters are connected to a precharge line. During operation, the source terminals of the pull-down transistors in the memory cell are precharged to “reset” the internal nodes of the memory cell to a predetermined state. Then, data can be stored by creating a small voltage difference between bit lines and coupling the bit lines to the internal nodes of the memory cell. In an alternative embodiment of the present invention, the pull-up transistors of the inverters are connected to a precharge line so that the source terminals of the pull-up transistors in the memory cell are precharged.
Another object of the present invention is to provide a RAM memory device that has relatively long word length but reduced power consumption.
A further object of the present invention is to provide a technique for reducing voltage swing on the memory array bit lines during a write operation.
Yet another object of the present invention is to provide a RAM memory device having a simple write operation.
One embodiment of the present invention provides a semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each inverter is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.


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European Search Report dated May 13, 1998 with annex on European Application No. 97 120943.

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