Low power, race free programmable logic arrays

Details Low power, race free programmable logic arrays Low power, race free programmable logic arrays

2007-04-30

2009-06-02

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S038000, C326S039000

Reexamination Certificate

active

07541832

ABSTRACT:
The present invention provides a PLA architecture where the AND plane is implemented with NAND logic. The OR plane may be implemented with various logic, but in one embodiment, the OR plane is implemented with NOR logic. The AND plane may have multiple sequential stages providing hierarchical NAND logic. The NAND logic may be broken into a hierarchy of NAND logic blocks. Each NAND logic block may include one or more series-connected NAND transistor stacks. Each transistor in the transistor stack may receive an input signal representing the product of a PLA clock signal and either a direct PLA input or the complement thereof. As such, the PLA clock is inherently integrated with the input signals that drive the various transistors of the NAND transistor stacks.

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