Low power quasi-static storage cell

Details Low power quasi-static storage cell Low power quasi-static storage cell

1979-06-15

1981-01-27

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365187, G11C 700, G11C 1140

Patent

active

042479193

ABSTRACT:
A semiconductor memory device forming a static type memory cell uses three field effect transistors. One is connected between a storage node and a bit line so it functions as an access transistor. The storage node is connected to a refresh node through a second transistor having its gate shorted to drain, and the third transistor connects the refresh node to a supply voltage. A voltage dependent capacitor connects the refresh node to a refresh clock. A logic 1 on the storage node turns on the third transistor and charges the refresh node, which turns on the capacitor so the refresh clock is coupled through to turn on the second transistor and refresh the storage node. When a logic 0 is stored, this will not happen.

REFERENCES:
patent: 4070653 (1978-01-01), Rao et al.
patent: 4161791 (1979-07-01), Leach
Shiga et al., "A Monostable CMOS RAM with Self-Refresh Mode, 1976 IEEE International Solid-State Circuits Conf., pp. 134-135, 2/19/76.

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