Low power programmable logic array assembly

Details Low power programmable logic array assembly Low power programmable logic array assembly

2001-08-17

2002-08-13

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S038000, C326S039000

Reexamination Certificate

active

06433577

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90109496, filed Apr. 20, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a type of programmable logic array circuit. More particularly, the present invention relates to a low power programmable logic array assembly.
2. Description of Related Art
FIG. 1
is a block diagram of a conventional programmable logic array (PLA). As shown in
FIG. 1
, a programmable logic array mainly includes five major blocks an input buffer
102
, an AND-plane circuit
104
, an inter-plane buffer
106
, an OR-plane circuit
108
and an output buffer
110
. The AND-plane circuit
104
and the OR-plane circuit
108
provide a sum-of-product (SOP) logic. On the other hand, the input buffer
102
, the inter-plane buffer
106
and the output buffer
110
provide necessary driving capability to the logic circuit. Normally, clock control signals are included to synchronize with an outside system.
A number of improved programmable logic array designs have also been developed. The following is a brief description of some of the improved PLA circuits.
A. Conventional Clock-delayed PLA
FIG. 2
is a circuit diagram of a 5×8×4 conventional clock-delayed PLA. As shown in
FIG. 2
, the clocked-delay PLA implements the Boolean functions Z
1
~Z
4
. The ‘5’ in the 5×8×4 PLA indicates that the number of input variables is five (a, b, c, d and e). The ‘8’ in the 5×8×4 PLA indicates that the number of product terms is eight (P1~P8). The ‘4’ in the 5×8×4 PLA indicates that the number of output values is four (Z
1
~Z
4
). Furthermore, the Boolean functions are as follows:
Z
1
=a{overscore (b)}{overscore (d)}e+{overscore (a)}{overscore (b)}{overscore (c)}{overscore (d)}{overscore (e)}+bc+de;
  (1)
Z
2
={overscore (a)}{overscore (c)}e;
  (2)
Z
3
=bc+de+{overscore (c)}{overscore (d)}{overscore (e)}+bd;
  (3)
Z
4
={overscore (a)}{overscore (c)}e+ce
  (4)
In
FIG. 2
, an external clock control signal &psgr; produces two in-phase internal clock control signals &psgr;
1
and &psgr;
1d
applied to the AND-plane circuit
104
and the OR-plane circuit
108
respectively. A path marked in gray color is a critical path for this circuit. A critical path is a route that includes the largest loading from an input terminal to an output terminal of the circuit and hence operating speed depends upon the critical path.
FIG. 3A
is a circuit taken from the critical path in FIG.
2
and
FIG. 3B
is a diagram showing a set of signal waveforms related to the circuit shown in FIG.
3
A. Note that the clock control signal used by the AND-plane circuit
318
and the OR-plane circuit
322
are different. If both the AND-plane circuit
318
and the OR-plane circuit
322
use the same clock control signal, signal at node
6
will be destroyed by the pre-charging signal at node
5
in the evaluation phase initialization. This will lead to data race errors shown as gray-marked area in FIG.
3
B. To prevent the data race errors, clocking signal to the OR-plane circuit
322
must be delayed. One must wait until the data at node
5
is stabilized before carrying out any evaluation actions. This is the reason why this type of PLA is called a clock-delayed PLA. Hence, the main disadvantage of the clock-delayed PLA is the delay of clocking signal to the OR-plane circuit
322
to prevent data racing.
In
FIG. 3B
, a few time parameters are defined for analyzing operating speed of such a circuit. The following is a list of various timing definitions.
(1) External access time (t
acc
): from the edge of the external clock signal &psgr; rising to a high potential to the signal at the output terminal changing potential;
(2) Internal access time (t
iacc
): from the edge of the internal clock signal &psgr;
1
rising to a high potential to the signal at the output changing potential; and
(3) Internal clocking time difference (t
d
): time difference between the internal clock signal &psgr;
1
and the internal clock signal &psgr;
1d
, obviously, if duty cycle of the clocking signal is 50%, the smallest operating cycle can be defined as twice the internal access time (t
iacc
).
As shown in
FIG. 3B
, the value of td can surely affect t
acc
and t
iacc
. Consequently, the critical path of a conventional clock-delayed circuit shown in
FIG. 3A
includes the AND function block
318
, the inter-plane buffer
320
, the OR function block
322
and the output buffer
324
. The large parasitic capacitors C
AND
, C′
AND
, C
inter
, C
OR
and C′
OR
along the critical path is a major reason for a slow-down of the operating speed in the circuit. Due to the absence of dc power consumption in a dynamic circuit, power is dominated mainly for dynamic power consumption. In general, the power consumption of a dynamic circuit is represented by
P
=
∑
i
=
1
n
⁢
α
i
⁢
C
i
⁢
V
DD
2
⁢
f
.
Here, &agr;
i
the switching probability of node i, C
i
is the lumped capacitance of node i, V
DD
is the operating voltage and f is the frequency. If V
DD
and f has fixed values, the only consideration is the values of &agr;
i
and C
i
. The product &agr;C is defined as the power factor (PF). The critical path shown in
FIG. 3A
can be used to evaluate the operating speed of the circuit. Because power consumption of the PLA circuit is related to the implemented Boolean functions, power consumption determined from the critical path is not equivalent to the power consumption of the entire circuit. To simplify estimation of power consumption, the critical path is still employed as a base with the incorporation of switching probability according to the blocks shown in FIG.
1
. Because the clocking signals are global signals, clocking signal is not included into the power consumption consideration.
The following is an observation of the power factors of various functional blocks.
(1) The input buffer
102
: if probability of the input signal is evenly distributed, &agr;
IN
can be represented by
1
2
·
1
2
=
1
4
,
and power factor of the input buffer
102
is &agr;
IN
C
IN
.
(2) The AND-plane circuit
104
and the inter-plane buffer region
106
: if the number of input is N, the switching probability of a dynamic NOR gate is
2
N
-
1
2
N
.
In other words, the switching probability of dynamic NOR gates in the AND-plane circuit
104
&agr;
AND
and &agr;′
AND
is
2
N
-
1
2
N
.
Because the inter-plane buffer region
106
will change according to the AND-plane circuit
104
, switching probability &agr;
inter
is
2
N
-
1
2
N
as well. If the number of inputs is very large, the value of &agr;
AND
, &agr;′
AND
and
60
inter
is close to one. Furthermore, due to the long interconnection wires and parasitic capacitors of transistors contribute to the capacitors C
AND
, C′
AND
, and C
inter
, these capacitance are relatively large. Therefore, the power factors including &agr;
AND
·C
AND
, &agr;′
AND
·C′
AND
, and &agr;
inter
·C
inter
of such components are a leading factor of large power consumption.
(3) The OR-plane circuit
108
. The switching probability in the OR-plane circuit
108
is mainly affected by the output from the inter-plane buffer
106
. Assume the OR-plane circuit
108
is an N-input dynamic NOR gate and p
i
is the probability of the i
th
input of the dynamic NOR gate being one, transition probability
α
OR
=
1
-
∏
i
=
1
N
⁢
 
⁢
(
1
-
p
i
)
.
Hence, &agr;
OR
·C
OR
is related to the input and the desired function.
B. Blair's PLA
FIG. 4A
is a circuit diagram showing a Blair's PLA and a critical path through the circuit.
FIG. 4B
is a timing diagram showing waveforms related to the signals in FIG.
4
A. Because the AND-plane circuit
418
of the Blair's PLA uses a pre-discharged pseudo-NMOS circuit, operating speed in the AND-plane circuit
418
is affected. Since the pseudo-NMOS

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