Low-power processor hint, such as from a pause instruction

Details Low-power processor hint, such as from a pause instruction Low-power processor hint, such as from a pause instruction

2007-01-02

2007-01-02

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

Reexamination Certificate

active

10759455

ABSTRACT:
A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.

REFERENCES:
patent: 5892959 (1999-04-01), Fung
patent: 6079025 (2000-06-01), Fung
patent: 6105142 (2000-08-01), Goff et al.
patent: 6128745 (2000-10-01), Anderson et al.
patent: 6308279 (2001-10-01), Toll et al.
patent: 6687838 (2004-02-01), Orenstien et al.

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