Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2001-03-12
2002-11-12
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S00100A, C331S025000, C327S157000, C327S159000
Reexamination Certificate
active
06480070
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a phase locked loop circuit for locking a clock signal to an input signal comprising a phase frequency detector for supplying up pulse signals and down pulse signals to a charge pump, which charge pump comprises a set of current sources and an idle path for maintaining current supplying transistors in the current sources in a current conductive state when no up an down signals are present.
A phase frequency detector and a charge pump are critical parts in synthesizers. When the synthesizer is locked the phase frequency detector delivers short up and down pulse signals to the charge pump. In the short period of time that an up pulse signal or down pulse signal lasts, of the order of one nanosecond, the charge pump should deliver equal up and down current pulses, respectively to its output. Standard charge pumps are limited by the time constant of switching on output current mirror transistors when changing state from off (no current) to saturation (current on). Because N- and PMOS react with different time constants additional delays must be included in the phase detector's feedback to compensate for such different time constants. The additional delays allow up or down currents to settle.
A drawback of a delay is increased noise in the synthesizer loop because of increased time of noise injection of the more or less conducting mirror transistors.
I. Young, “A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors”, JSSC, 11.1992, pp 1599 and M. Johnson, “A variable delay line PLL for CPU-coprocessor synchronization”, JSSC, 10.1998, pp 1218-1223 describe using a dummy path to prevent the mirror transistors leaving the saturation region. The cut in the mirror transistors is kept stable by switching the current over a dummy path while neither up nor down path is active. This known solution greatly reduces or avoids the delay needed in the phase frequency detector.
However, a drawback of this known solution is increased power because the tail current is always flowing.
SUMMARY OF THE INVENTION
It is an object of the present invention to lower the amount of power needed to control a charge pump wit an idle path.
A phase locked loop circuit according to the invention thereto is characterized in that first means are present for enabling and disabling the idle path in response to idle path enabling and idle path disabling signals, respectively and in that second means are present for, shortly before an appearance of up and down pulse signals, respectively generating an idle path enabling signal and for, shortly after the respective up and down pulse signals have disappeared, generating an idle path disabling signal.
Because the up and down pulse signals themselves last only for a very short time relative to a substantially larger period of time between subsequent up and down pulse signals a great power saving is achieved.
REFERENCES:
patent: 5359299 (1994-10-01), Webster
“A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, by I.A. Young et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992.
“A Variable Delay Line PLL for CPU-Coprocessor Synchronization”, by M. G. Johnson et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
“A Wide-Band Tuning System for Fully Integrated Satellite Receivers”, by C. Vaucher et al., IEEE Journal of Solid-State Circuits, vol. 33, No. 7, Jul. 1998.
Koninklijke Phillips Electronics N.V.
Mis David
Waxler Aaron
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