Low power memory subsystem with progressive non-volatility

Details Low power memory subsystem with progressive non-volatility Low power memory subsystem with progressive non-volatility

2007-10-02

2007-10-02

Hu, Shouxiang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S320000

Reexamination Certificate

active

11066905

ABSTRACT:
The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells of each array has a tunnel layer under an embedded trap layer. Each array has memory cells with a different tunnel layer thickness to change the read/write speeds and charge retention times for that array.

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patent: 2005/0199944 (2005-09-01), Chen et al.
patent: 6-5822 (1994-01-01), None
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Dana Lee et al.; Vertical floating-gate 4.5F2Split-gate NOR Flash Memory at 110nm Node; Silicon Storage Technology, Inc. and PowerChip Semiconductor Corporation; 2004 Symposium on VLSI Technology Digest of Technical Papers; pp. 72-73.

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