Low power memory architecture

Details Low power memory architecture Low power memory architecture

2006-02-28

2009-06-30

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C365S227000, C365S230030

Reexamination Certificate

active

07555659

ABSTRACT:
A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.

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